
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12114274
[patent_doc_number] => 09870267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-16
[patent_title] => 'Virtual vector processing'
[patent_app_type] => utility
[patent_app_number] => 11/386443
[patent_app_country] => US
[patent_app_date] => 2006-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6359
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11386443
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/386443 | Virtual vector processing | Mar 21, 2006 | Issued |
Array
(
[id] => 4539873
[patent_doc_number] => 07953959
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-31
[patent_title] => 'Processor'
[patent_app_type] => utility
[patent_app_number] => 11/916474
[patent_app_country] => US
[patent_app_date] => 2006-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 40
[patent_no_of_words] => 12160
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/953/07953959.pdf
[firstpage_image] =>[orig_patent_app_number] => 11916474
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/916474 | Processor | Mar 8, 2006 | Issued |
Array
(
[id] => 4741711
[patent_doc_number] => 20080235364
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'Method and apparatus for using dynamic workload characteristics to control CPU frequency and voltage scaling'
[patent_app_type] => utility
[patent_app_number] => 11/370254
[patent_app_country] => US
[patent_app_date] => 2006-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4788
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20080235364.pdf
[firstpage_image] =>[orig_patent_app_number] => 11370254
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/370254 | Method and apparatus for using dynamic workload characteristics to control CPU frequency and voltage scaling | Mar 6, 2006 | Issued |
Array
(
[id] => 5286754
[patent_doc_number] => 20090100429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'Dual Mode Operating System For A Computing Device'
[patent_app_type] => utility
[patent_app_number] => 11/817381
[patent_app_country] => US
[patent_app_date] => 2006-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3844
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0100/20090100429.pdf
[firstpage_image] =>[orig_patent_app_number] => 11817381
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/817381 | Dual mode operating system for a computing device | Feb 28, 2006 | Issued |
Array
(
[id] => 5878899
[patent_doc_number] => 20060168309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Symbol parsing architecture'
[patent_app_type] => utility
[patent_app_number] => 11/365051
[patent_app_country] => US
[patent_app_date] => 2006-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9539
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0168/20060168309.pdf
[firstpage_image] =>[orig_patent_app_number] => 11365051
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/365051 | Symbol parsing architecture | Feb 27, 2006 | Issued |
Array
(
[id] => 5179161
[patent_doc_number] => 20070180221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-02
[patent_title] => 'Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines'
[patent_app_type] => utility
[patent_app_number] => 11/345922
[patent_app_country] => US
[patent_app_date] => 2006-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10186
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0180/20070180221.pdf
[firstpage_image] =>[orig_patent_app_number] => 11345922
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/345922 | Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines | Feb 1, 2006 | Issued |
Array
(
[id] => 5761735
[patent_doc_number] => 20060212680
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-21
[patent_title] => 'Methods and apparatus for dynamic prediction by software'
[patent_app_type] => utility
[patent_app_number] => 11/344403
[patent_app_country] => US
[patent_app_date] => 2006-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4191
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20060212680.pdf
[firstpage_image] =>[orig_patent_app_number] => 11344403
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/344403 | Methods and apparatus for dynamic prediction by software | Jan 30, 2006 | Issued |
Array
(
[id] => 9029614
[patent_doc_number] => 08539211
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-17
[patent_title] => 'Allocating registers for loop variables in a multi-threaded processor'
[patent_app_type] => utility
[patent_app_number] => 11/814801
[patent_app_country] => US
[patent_app_date] => 2006-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2243
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11814801
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/814801 | Allocating registers for loop variables in a multi-threaded processor | Jan 16, 2006 | Issued |
Array
(
[id] => 5633482
[patent_doc_number] => 20060149953
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Conditional execution per lane'
[patent_app_type] => utility
[patent_app_number] => 11/327453
[patent_app_country] => US
[patent_app_date] => 2006-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 10726
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0149/20060149953.pdf
[firstpage_image] =>[orig_patent_app_number] => 11327453
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/327453 | Conditional execution per lane | Jan 8, 2006 | Issued |
Array
(
[id] => 374920
[patent_doc_number] => 07475228
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-06
[patent_title] => 'Ensuring progress in a system that supports execution of obstruction-free operations'
[patent_app_type] => utility
[patent_app_number] => 11/325062
[patent_app_country] => US
[patent_app_date] => 2006-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5777
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/475/07475228.pdf
[firstpage_image] =>[orig_patent_app_number] => 11325062
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/325062 | Ensuring progress in a system that supports execution of obstruction-free operations | Jan 2, 2006 | Issued |
Array
(
[id] => 5553923
[patent_doc_number] => 20090287909
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-19
[patent_title] => 'Dynamically Estimating Lifetime of a Semiconductor Device'
[patent_app_type] => utility
[patent_app_number] => 12/086357
[patent_app_country] => US
[patent_app_date] => 2005-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5549
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0287/20090287909.pdf
[firstpage_image] =>[orig_patent_app_number] => 12086357
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/086357 | Dynamically estimating lifetime of a semiconductor device | Dec 29, 2005 | Issued |
Array
(
[id] => 5024735
[patent_doc_number] => 20070150702
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-28
[patent_title] => 'Processor'
[patent_app_type] => utility
[patent_app_number] => 11/318042
[patent_app_country] => US
[patent_app_date] => 2005-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 7066
[patent_no_of_claims] => 88
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0150/20070150702.pdf
[firstpage_image] =>[orig_patent_app_number] => 11318042
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/318042 | Processor | Dec 22, 2005 | Abandoned |
Array
(
[id] => 4586542
[patent_doc_number] => 07849297
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-07
[patent_title] => 'Software emulation of directed exceptions in a multithreading processor'
[patent_app_type] => utility
[patent_app_number] => 11/313272
[patent_app_country] => US
[patent_app_date] => 2005-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 26
[patent_no_of_words] => 17518
[patent_no_of_claims] => 68
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/849/07849297.pdf
[firstpage_image] =>[orig_patent_app_number] => 11313272
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/313272 | Software emulation of directed exceptions in a multithreading processor | Dec 19, 2005 | Issued |
Array
(
[id] => 86644
[patent_doc_number] => 07747842
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-06-29
[patent_title] => 'Configurable output buffer ganging for a parallel processor'
[patent_app_type] => utility
[patent_app_number] => 11/311993
[patent_app_country] => US
[patent_app_date] => 2005-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 10299
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/747/07747842.pdf
[firstpage_image] =>[orig_patent_app_number] => 11311993
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/311993 | Configurable output buffer ganging for a parallel processor | Dec 18, 2005 | Issued |
Array
(
[id] => 213331
[patent_doc_number] => 07624250
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-24
[patent_title] => 'Heterogeneous multi-core processor having dedicated connections between processor cores'
[patent_app_type] => utility
[patent_app_number] => 11/294809
[patent_app_country] => US
[patent_app_date] => 2005-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3910
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/624/07624250.pdf
[firstpage_image] =>[orig_patent_app_number] => 11294809
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/294809 | Heterogeneous multi-core processor having dedicated connections between processor cores | Dec 4, 2005 | Issued |
Array
(
[id] => 343155
[patent_doc_number] => 07502916
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-10
[patent_title] => 'Processing arrangement, memory card device and method for operating and manufacturing a processing arrangement'
[patent_app_type] => utility
[patent_app_number] => 11/292948
[patent_app_country] => US
[patent_app_date] => 2005-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6075
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/502/07502916.pdf
[firstpage_image] =>[orig_patent_app_number] => 11292948
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/292948 | Processing arrangement, memory card device and method for operating and manufacturing a processing arrangement | Dec 1, 2005 | Issued |
Array
(
[id] => 374923
[patent_doc_number] => 07475231
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-01-06
[patent_title] => 'Loop detection and capture in the instruction queue'
[patent_app_type] => utility
[patent_app_number] => 11/273691
[patent_app_country] => US
[patent_app_date] => 2005-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5573
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/475/07475231.pdf
[firstpage_image] =>[orig_patent_app_number] => 11273691
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/273691 | Loop detection and capture in the instruction queue | Nov 13, 2005 | Issued |
Array
(
[id] => 4973220
[patent_doc_number] => 20070113223
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-17
[patent_title] => 'Dynamic instruction sequence selection during scheduling'
[patent_app_type] => utility
[patent_app_number] => 11/274602
[patent_app_country] => US
[patent_app_date] => 2005-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7755
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20070113223.pdf
[firstpage_image] =>[orig_patent_app_number] => 11274602
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/274602 | Dynamic instruction sequence selection during scheduling | Nov 13, 2005 | Issued |
Array
(
[id] => 914593
[patent_doc_number] => 07330964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-02-12
[patent_title] => 'Microprocessor with independent SIMD loop buffer'
[patent_app_type] => utility
[patent_app_number] => 11/273493
[patent_app_country] => US
[patent_app_date] => 2005-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3480
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/330/07330964.pdf
[firstpage_image] =>[orig_patent_app_number] => 11273493
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/273493 | Microprocessor with independent SIMD loop buffer | Nov 13, 2005 | Issued |
Array
(
[id] => 868799
[patent_doc_number] => 07370179
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-06
[patent_title] => 'Microprocessor'
[patent_app_type] => utility
[patent_app_number] => 11/268386
[patent_app_country] => US
[patent_app_date] => 2005-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4027
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/370/07370179.pdf
[firstpage_image] =>[orig_patent_app_number] => 11268386
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/268386 | Microprocessor | Nov 6, 2005 | Issued |