Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5305953 [patent_doc_number] => 20090300605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'VIRTUAL COMPUTING INFRASTRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/718196 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14921 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300605.pdf [firstpage_image] =>[orig_patent_app_number] => 11718196 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/718196
Managing virtual overlay infrastructures Oct 27, 2005 Issued
Array ( [id] => 596420 [patent_doc_number] => 07454599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Selecting multiple threads for substantially concurrent processing' [patent_app_type] => utility [patent_app_number] => 11/229808 [patent_app_country] => US [patent_app_date] => 2005-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4891 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454599.pdf [firstpage_image] =>[orig_patent_app_number] => 11229808 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/229808
Selecting multiple threads for substantially concurrent processing Sep 18, 2005 Issued
Array ( [id] => 4854540 [patent_doc_number] => 20080320283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Programmable Data Processor for a Variable Length \nEncoder/Decoder' [patent_app_type] => utility [patent_app_number] => 11/575318 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6394 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320283.pdf [firstpage_image] =>[orig_patent_app_number] => 11575318 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/575318
Programmable data processor for a variable length encoder/decoder Sep 14, 2005 Issued
Array ( [id] => 362552 [patent_doc_number] => 07487331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Programming a digital processor with a single connection' [patent_app_type] => utility [patent_app_number] => 11/227884 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2133 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487331.pdf [firstpage_image] =>[orig_patent_app_number] => 11227884 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227884
Programming a digital processor with a single connection Sep 14, 2005 Issued
Array ( [id] => 5058633 [patent_doc_number] => 20070061555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Call return tracking technique' [patent_app_type] => utility [patent_app_number] => 11/229177 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3978 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061555.pdf [firstpage_image] =>[orig_patent_app_number] => 11229177 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/229177
Call return tracking technique Sep 14, 2005 Abandoned
Array ( [id] => 4854530 [patent_doc_number] => 20080320273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Interconnections in Simd Processor Architectures' [patent_app_type] => utility [patent_app_number] => 11/575068 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2395 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320273.pdf [firstpage_image] =>[orig_patent_app_number] => 11575068 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/575068
Interconnections in SIMD processor architectures Sep 7, 2005 Issued
Array ( [id] => 5896457 [patent_doc_number] => 20060004996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Macroscalar processor architecture' [patent_app_type] => utility [patent_app_number] => 11/219622 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 70 [patent_no_of_words] => 38373 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20060004996.pdf [firstpage_image] =>[orig_patent_app_number] => 11219622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/219622
Macroscalar processor architecture Aug 31, 2005 Issued
Array ( [id] => 5809394 [patent_doc_number] => 20060095750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Processes, circuits, devices, and systems for branch prediction and other processor improvements' [patent_app_type] => utility [patent_app_number] => 11/210354 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 34085 [patent_no_of_claims] => 109 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095750.pdf [firstpage_image] =>[orig_patent_app_number] => 11210354 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/210354
Processes, circuits, devices, and systems for branch prediction and other processor improvements Aug 23, 2005 Issued
Array ( [id] => 5610094 [patent_doc_number] => 20060271610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Digital signal processor having reconfigurable data paths' [patent_app_type] => utility [patent_app_number] => 11/192006 [patent_app_country] => US [patent_app_date] => 2005-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2698 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20060271610.pdf [firstpage_image] =>[orig_patent_app_number] => 11192006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/192006
Digital signal processor having reconfigurable data paths Jul 28, 2005 Abandoned
Array ( [id] => 927458 [patent_doc_number] => 07318144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-08 [patent_title] => 'Apparatus and method for interconnecting a processor to co-processors using shared memory' [patent_app_type] => utility [patent_app_number] => 11/182141 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 15704 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/318/07318144.pdf [firstpage_image] =>[orig_patent_app_number] => 11182141 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/182141
Apparatus and method for interconnecting a processor to co-processors using shared memory Jul 14, 2005 Issued
Array ( [id] => 5739802 [patent_doc_number] => 20060010193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Parser table/production rule table configuration using CAM and SRAM' [patent_app_type] => utility [patent_app_number] => 11/181527 [patent_app_country] => US [patent_app_date] => 2005-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9538 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20060010193.pdf [firstpage_image] =>[orig_patent_app_number] => 11181527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/181527
Parser table/production rule table configuration using CAM and SRAM Jul 13, 2005 Issued
Array ( [id] => 4889000 [patent_doc_number] => 20080263332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Data Processing Apparatus and Method for Accelerating Execution Subgraphs' [patent_app_type] => utility [patent_app_number] => 11/884362 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10537 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263332.pdf [firstpage_image] =>[orig_patent_app_number] => 11884362 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/884362
Data processing apparatus and method for accelerating execution of subgraphs Jun 21, 2005 Issued
Array ( [id] => 7057340 [patent_doc_number] => 20050278515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Information processing apparatus, microcomputer, and electronic computer' [patent_app_type] => utility [patent_app_number] => 11/149494 [patent_app_country] => US [patent_app_date] => 2005-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4685 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278515.pdf [firstpage_image] =>[orig_patent_app_number] => 11149494 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/149494
Information processing apparatus, microcomputer, and electronic computer Jun 8, 2005 Issued
Array ( [id] => 598206 [patent_doc_number] => 07451297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Computing system and method that determines current configuration dependent on operand input from another configuration' [patent_app_type] => utility [patent_app_number] => 11/143307 [patent_app_country] => US [patent_app_date] => 2005-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 54 [patent_no_of_words] => 22365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/451/07451297.pdf [firstpage_image] =>[orig_patent_app_number] => 11143307 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/143307
Computing system and method that determines current configuration dependent on operand input from another configuration May 31, 2005 Issued
Array ( [id] => 7112765 [patent_doc_number] => 20050210221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Microcomputer and microcomputer system' [patent_app_type] => utility [patent_app_number] => 11/130200 [patent_app_country] => US [patent_app_date] => 2005-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 27737 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20050210221.pdf [firstpage_image] =>[orig_patent_app_number] => 11130200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/130200
Microcomputer and microcomputer system May 16, 2005 Abandoned
Array ( [id] => 6927500 [patent_doc_number] => 20050240757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Control program product and data processing system' [patent_app_type] => utility [patent_app_number] => 11/103345 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14216 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20050240757.pdf [firstpage_image] =>[orig_patent_app_number] => 11103345 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/103345
Control program product and data processing system Apr 10, 2005 Abandoned
Array ( [id] => 6946660 [patent_doc_number] => 20050198477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Synchronous network traffic processor' [patent_app_type] => utility [patent_app_number] => 11/102977 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11648 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198477.pdf [firstpage_image] =>[orig_patent_app_number] => 11102977 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/102977
Synchronous network traffic processor Apr 10, 2005 Issued
Array ( [id] => 7047050 [patent_doc_number] => 20050251645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Method and apparatus for staggering execution of an instruction' [patent_app_type] => utility [patent_app_number] => 11/103702 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6933 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20050251645.pdf [firstpage_image] =>[orig_patent_app_number] => 11103702 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/103702
Method and apparatus for staggering execution of an instruction Apr 10, 2005 Issued
Array ( [id] => 87659 [patent_doc_number] => 07743233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Sequencer address management' [patent_app_type] => utility [patent_app_number] => 11/100032 [patent_app_country] => US [patent_app_date] => 2005-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 19501 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743233.pdf [firstpage_image] =>[orig_patent_app_number] => 11100032 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/100032
Sequencer address management Apr 4, 2005 Issued
Array ( [id] => 5701867 [patent_doc_number] => 20060218552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Method and apparatus for extending operations of an application in a data processing system' [patent_app_type] => utility [patent_app_number] => 11/089987 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20060218552.pdf [firstpage_image] =>[orig_patent_app_number] => 11089987 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089987
Method and apparatus for extending operations of an application in a data processing system Mar 23, 2005 Issued
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