Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 388585 [patent_doc_number] => 07305541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Compression of program instructions using advanced sequential correlation' [patent_app_type] => utility [patent_app_number] => 11/086124 [patent_app_country] => US [patent_app_date] => 2005-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9687 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305541.pdf [firstpage_image] =>[orig_patent_app_number] => 11086124 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/086124
Compression of program instructions using advanced sequential correlation Mar 20, 2005 Issued
Array ( [id] => 5789018 [patent_doc_number] => 20060206731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Methods and apparatus for improving processing performance by controlling latch points' [patent_app_type] => utility [patent_app_number] => 11/079565 [patent_app_country] => US [patent_app_date] => 2005-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9100 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20060206731.pdf [firstpage_image] =>[orig_patent_app_number] => 11079565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/079565
Methods and apparatus for improving processing performance by controlling latch points Mar 13, 2005 Issued
Array ( [id] => 7177053 [patent_doc_number] => 20050203928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Register move instruction for section select of source operand' [patent_app_type] => utility [patent_app_number] => 11/072777 [patent_app_country] => US [patent_app_date] => 2005-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9586 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20050203928.pdf [firstpage_image] =>[orig_patent_app_number] => 11072777 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/072777
Register move instruction for section select of source operand Mar 3, 2005 Issued
Array ( [id] => 7006794 [patent_doc_number] => 20050172107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Replay instruction morphing' [patent_app_type] => utility [patent_app_number] => 11/069004 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4279 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172107.pdf [firstpage_image] =>[orig_patent_app_number] => 11069004 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/069004
Replay instruction morphing Feb 27, 2005 Issued
Array ( [id] => 7076800 [patent_doc_number] => 20050149590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Method and system for performing permutations with bit permutation instructions' [patent_app_type] => utility [patent_app_number] => 11/058819 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 12711 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20050149590.pdf [firstpage_image] =>[orig_patent_app_number] => 11058819 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058819
Method and system for performing permutations with bit permutation instructions Feb 15, 2005 Issued
Array ( [id] => 5739918 [patent_doc_number] => 20060010309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Selective execution of deferred instructions in a processor that supports speculative execution' [patent_app_type] => utility [patent_app_number] => 11/058522 [patent_app_country] => US [patent_app_date] => 2005-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4924 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20060010309.pdf [firstpage_image] =>[orig_patent_app_number] => 11058522 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058522
Selective execution of deferred instructions in a processor that supports speculative execution Feb 13, 2005 Issued
Array ( [id] => 7077163 [patent_doc_number] => 20050149699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Variable length instruction pipeline' [patent_app_type] => utility [patent_app_number] => 11/053096 [patent_app_country] => US [patent_app_date] => 2005-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4343 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20050149699.pdf [firstpage_image] =>[orig_patent_app_number] => 11053096 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/053096
Variable length instruction pipeline Feb 6, 2005 Issued
Array ( [id] => 7255274 [patent_doc_number] => 20050273580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Avoiding register RAW hazards when returning from speculative execution' [patent_app_type] => utility [patent_app_number] => 11/053382 [patent_app_country] => US [patent_app_date] => 2005-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4814 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20050273580.pdf [firstpage_image] =>[orig_patent_app_number] => 11053382 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/053382
Avoiding register RAW hazards when returning from speculative execution Feb 6, 2005 Issued
Array ( [id] => 925052 [patent_doc_number] => 07320063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-15 [patent_title] => 'Synchronization primitives for flexible scheduling of functional unit operations' [patent_app_type] => utility [patent_app_number] => 11/051431 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 15001 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/320/07320063.pdf [firstpage_image] =>[orig_patent_app_number] => 11051431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/051431
Synchronization primitives for flexible scheduling of functional unit operations Feb 3, 2005 Issued
Array ( [id] => 265528 [patent_doc_number] => 07571302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-04 [patent_title] => 'Dynamic data dependence tracking and its application to branch prediction' [patent_app_type] => utility [patent_app_number] => 11/050454 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 8032 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/571/07571302.pdf [firstpage_image] =>[orig_patent_app_number] => 11050454 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/050454
Dynamic data dependence tracking and its application to branch prediction Feb 3, 2005 Issued
Array ( [id] => 5668742 [patent_doc_number] => 20060174092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Fetch-side instruction dispatch group formation' [patent_app_type] => utility [patent_app_number] => 11/050367 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20060174092.pdf [firstpage_image] =>[orig_patent_app_number] => 11050367 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/050367
Fetch-side instruction dispatch group formation Feb 2, 2005 Issued
Array ( [id] => 5878909 [patent_doc_number] => 20060168314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Intellectual property module for system-on-chip' [patent_app_type] => utility [patent_app_number] => 11/048595 [patent_app_country] => US [patent_app_date] => 2005-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1792 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20060168314.pdf [firstpage_image] =>[orig_patent_app_number] => 11048595 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/048595
Intellectual property module for system-on-chip Jan 31, 2005 Issued
Array ( [id] => 7006897 [patent_doc_number] => 20050172210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Add-compare-select accelerator using pre-compare-select-add operation' [patent_app_type] => utility [patent_app_number] => 11/049436 [patent_app_country] => US [patent_app_date] => 2005-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15182 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172210.pdf [firstpage_image] =>[orig_patent_app_number] => 11049436 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049436
Add-compare-select accelerator using pre-compare-select-add operation Jan 31, 2005 Abandoned
Array ( [id] => 245077 [patent_doc_number] => 07590821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Digital signal processing integrated circuit with I/O connections' [patent_app_type] => utility [patent_app_number] => 10/588889 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4914 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590821.pdf [firstpage_image] =>[orig_patent_app_number] => 10588889 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/588889
Digital signal processing integrated circuit with I/O connections Jan 30, 2005 Issued
Array ( [id] => 900147 [patent_doc_number] => 07343482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Program subgraph identification' [patent_app_type] => utility [patent_app_number] => 11/048663 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 9902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/343/07343482.pdf [firstpage_image] =>[orig_patent_app_number] => 11048663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/048663
Program subgraph identification Jan 30, 2005 Issued
Array ( [id] => 927454 [patent_doc_number] => 07318143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-08 [patent_title] => 'Reuseable configuration data' [patent_app_type] => utility [patent_app_number] => 11/044734 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 10994 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/318/07318143.pdf [firstpage_image] =>[orig_patent_app_number] => 11044734 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/044734
Reuseable configuration data Jan 27, 2005 Issued
Array ( [id] => 582331 [patent_doc_number] => 07162613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Mechanism for processing speculative LL and SC instructions in a pipelined processor' [patent_app_type] => utility [patent_app_number] => 11/046454 [patent_app_country] => US [patent_app_date] => 2005-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8845 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/162/07162613.pdf [firstpage_image] =>[orig_patent_app_number] => 11046454 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/046454
Mechanism for processing speculative LL and SC instructions in a pipelined processor Jan 27, 2005 Issued
Array ( [id] => 5879153 [patent_doc_number] => 20060168434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Method and system of aligning execution point of duplicate copies of a user program by copying memory stores' [patent_app_type] => utility [patent_app_number] => 11/042427 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9319 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20060168434.pdf [firstpage_image] =>[orig_patent_app_number] => 11042427 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042427
Method and system of aligning execution point of duplicate copies of a user program by copying memory stores Jan 24, 2005 Issued
Array ( [id] => 4556867 [patent_doc_number] => 07890738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Method and logical apparatus for managing processing system resource use for speculative execution' [patent_app_type] => utility [patent_app_number] => 11/039498 [patent_app_country] => US [patent_app_date] => 2005-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3088 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/890/07890738.pdf [firstpage_image] =>[orig_patent_app_number] => 11039498 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/039498
Method and logical apparatus for managing processing system resource use for speculative execution Jan 19, 2005 Issued
Array ( [id] => 5696259 [patent_doc_number] => 20060156406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Secure hardware personalization service' [patent_app_type] => utility [patent_app_number] => 11/035337 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4389 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156406.pdf [firstpage_image] =>[orig_patent_app_number] => 11035337 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/035337
Secure hardware personalization service Jan 12, 2005 Issued
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