Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 234896 [patent_doc_number] => 07600101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Multithreaded hardware systems and methods' [patent_app_type] => utility [patent_app_number] => 11/034464 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4190 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/600/07600101.pdf [firstpage_image] =>[orig_patent_app_number] => 11034464 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034464
Multithreaded hardware systems and methods Jan 12, 2005 Issued
Array ( [id] => 146586 [patent_doc_number] => 07689814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Methods and apparatus for disabling error countermeasures in a processing system' [patent_app_type] => utility [patent_app_number] => 11/016797 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10797 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689814.pdf [firstpage_image] =>[orig_patent_app_number] => 11016797 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/016797
Methods and apparatus for disabling error countermeasures in a processing system Dec 19, 2004 Issued
Array ( [id] => 7107262 [patent_doc_number] => 20050108510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Register file backup queue' [patent_app_type] => utility [patent_app_number] => 10/999005 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3686 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108510.pdf [firstpage_image] =>[orig_patent_app_number] => 10999005 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999005
Register file backup queue Nov 29, 2004 Issued
Array ( [id] => 820032 [patent_doc_number] => 07412592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Branch instruction control apparatus and control method' [patent_app_type] => utility [patent_app_number] => 10/994603 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8378 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/412/07412592.pdf [firstpage_image] =>[orig_patent_app_number] => 10994603 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/994603
Branch instruction control apparatus and control method Nov 22, 2004 Issued
Array ( [id] => 6946641 [patent_doc_number] => 20050198467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Method and apparatus for management of control flow in a SIMD device' [patent_app_type] => utility [patent_app_number] => 10/996269 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6517 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198467.pdf [firstpage_image] =>[orig_patent_app_number] => 10996269 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/996269
Method and apparatus for management of control flow in a SIMD device Nov 22, 2004 Issued
Array ( [id] => 595321 [patent_doc_number] => 07457940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'System and method for managing data' [patent_app_type] => utility [patent_app_number] => 10/989088 [patent_app_country] => US [patent_app_date] => 2004-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6125 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/457/07457940.pdf [firstpage_image] =>[orig_patent_app_number] => 10989088 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989088
System and method for managing data Nov 15, 2004 Issued
Array ( [id] => 17453 [patent_doc_number] => 07805594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Multithread processor and register control method' [patent_app_type] => utility [patent_app_number] => 10/986142 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6120 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/805/07805594.pdf [firstpage_image] =>[orig_patent_app_number] => 10986142 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/986142
Multithread processor and register control method Nov 11, 2004 Issued
Array ( [id] => 600325 [patent_doc_number] => 07437535 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-14 [patent_title] => 'Method and apparatus for issuing a command to store an instruction and load resultant data in a microcontroller' [patent_app_type] => utility [patent_app_number] => 10/980141 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 6536 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/437/07437535.pdf [firstpage_image] =>[orig_patent_app_number] => 10980141 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/980141
Method and apparatus for issuing a command to store an instruction and load resultant data in a microcontroller Oct 31, 2004 Issued
Array ( [id] => 7222748 [patent_doc_number] => 20050055537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Multiprocessor computer architecture incorporating a pluralityof memory algorithm processors in the memory subsystem' [patent_app_type] => utility [patent_app_number] => 10/969635 [patent_app_country] => US [patent_app_date] => 2004-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3376 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20050055537.pdf [firstpage_image] =>[orig_patent_app_number] => 10969635 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/969635
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem Oct 19, 2004 Issued
Array ( [id] => 4586478 [patent_doc_number] => 07849289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Distributed memory type information processing system' [patent_app_type] => utility [patent_app_number] => 10/595542 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 46 [patent_no_of_words] => 16714 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849289.pdf [firstpage_image] =>[orig_patent_app_number] => 10595542 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/595542
Distributed memory type information processing system Oct 18, 2004 Issued
Array ( [id] => 7260003 [patent_doc_number] => 20050076188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Data processor' [patent_app_type] => utility [patent_app_number] => 10/952913 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6589 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20050076188.pdf [firstpage_image] =>[orig_patent_app_number] => 10952913 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/952913
Data processor Sep 29, 2004 Issued
Array ( [id] => 5809384 [patent_doc_number] => 20060095740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Apparatus and methods for utilization of splittable execution units of a processor' [patent_app_type] => utility [patent_app_number] => 10/950690 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11745 [patent_no_of_claims] => 82 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095740.pdf [firstpage_image] =>[orig_patent_app_number] => 10950690 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950690
Apparatus and methods for utilization of splittable execution units of a processor Sep 27, 2004 Issued
Array ( [id] => 5809386 [patent_doc_number] => 20060095742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method and apparatus for using predicates in a processing device' [patent_app_type] => utility [patent_app_number] => 10/953808 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6765 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095742.pdf [firstpage_image] =>[orig_patent_app_number] => 10953808 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/953808
Method and apparatus for using predicates in a processing device Sep 27, 2004 Issued
Array ( [id] => 5830441 [patent_doc_number] => 20060064445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'System and method for specifying an immediate value in an instruction' [patent_app_type] => utility [patent_app_number] => 10/944310 [patent_app_country] => US [patent_app_date] => 2004-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4445 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20060064445.pdf [firstpage_image] =>[orig_patent_app_number] => 10944310 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/944310
System and method for specifying an immediate value in an instruction Sep 16, 2004 Issued
Array ( [id] => 469360 [patent_doc_number] => 07240182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'System and method for providing a persistent function server' [patent_app_type] => utility [patent_app_number] => 10/942432 [patent_app_country] => US [patent_app_date] => 2004-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240182.pdf [firstpage_image] =>[orig_patent_app_number] => 10942432 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/942432
System and method for providing a persistent function server Sep 15, 2004 Issued
Array ( [id] => 5809383 [patent_doc_number] => 20060095739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'SIMD processor executing min/max instructions' [patent_app_type] => utility [patent_app_number] => 10/940123 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4893 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095739.pdf [firstpage_image] =>[orig_patent_app_number] => 10940123 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/940123
SIMD processor executing min/max instructions Sep 12, 2004 Issued
Array ( [id] => 458041 [patent_doc_number] => 07249247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Common feature mode for microprocessors in a multiple microprocessor system' [patent_app_type] => utility [patent_app_number] => 10/940394 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6723 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/249/07249247.pdf [firstpage_image] =>[orig_patent_app_number] => 10940394 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/940394
Common feature mode for microprocessors in a multiple microprocessor system Sep 12, 2004 Issued
Array ( [id] => 877566 [patent_doc_number] => 07363473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'System for dynamic service provisioning' [patent_app_type] => utility [patent_app_number] => 10/938141 [patent_app_country] => US [patent_app_date] => 2004-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3444 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/363/07363473.pdf [firstpage_image] =>[orig_patent_app_number] => 10938141 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/938141
System for dynamic service provisioning Sep 9, 2004 Issued
Array ( [id] => 245084 [patent_doc_number] => 07590828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Processing a data word in a plurality of processing cycles' [patent_app_type] => utility [patent_app_number] => 11/660896 [patent_app_country] => US [patent_app_date] => 2004-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590828.pdf [firstpage_image] =>[orig_patent_app_number] => 11660896 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/660896
Processing a data word in a plurality of processing cycles Sep 7, 2004 Issued
Array ( [id] => 806140 [patent_doc_number] => 07424599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor' [patent_app_type] => utility [patent_app_number] => 10/929097 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13873 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/424/07424599.pdf [firstpage_image] =>[orig_patent_app_number] => 10929097 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929097
Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor Aug 26, 2004 Issued
Menu