
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 839897
[patent_doc_number] => 07395419
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-07-01
[patent_title] => 'Macroscalar processor architecture'
[patent_app_type] => utility
[patent_app_number] => 10/831615
[patent_app_country] => US
[patent_app_date] => 2004-04-23
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[pdf_file] => patents/07/395/07395419.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/831615 | Macroscalar processor architecture | Apr 22, 2004 | Issued |
Array
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[patent_issue_date] => 2009-06-30
[patent_title] => 'Multiple data hazards detection and resolution unit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/830244 | Multiple data hazards detection and resolution unit | Apr 21, 2004 | Issued |
Array
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[patent_issue_date] => 2006-09-19
[patent_title] => 'Data processor'
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Array
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[patent_title] => 'Method and system to provide user-level multithreading'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/816103 | Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution | Mar 30, 2004 | Issued |
Array
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[patent_title] => 'Emptying packed data state during execution of packed data instructions'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/805609 | Emptying packed data state during execution of packed data instructions | Mar 18, 2004 | Issued |
Array
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[patent_title] => 'Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/780083 | Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unit | Feb 16, 2004 | Issued |
Array
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[patent_title] => 'Chip multiprocessor for media applications'
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Array
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[patent_title] => 'Apparatus and method for performing a detached load operation in a pipeline microprocessor'
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Array
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[patent_title] => 'Thread ID in a multithreaded processor'
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Array
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[patent_title] => 'Thread-aware instruction fetching in a multithreaded embedded processor'
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