Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 839897 [patent_doc_number] => 07395419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-01 [patent_title] => 'Macroscalar processor architecture' [patent_app_type] => utility [patent_app_number] => 10/831615 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 41 [patent_no_of_words] => 25143 [patent_no_of_claims] => 101 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395419.pdf [firstpage_image] =>[orig_patent_app_number] => 10831615 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/831615
Macroscalar processor architecture Apr 22, 2004 Issued
Array ( [id] => 283978 [patent_doc_number] => 07555634 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-30 [patent_title] => 'Multiple data hazards detection and resolution unit' [patent_app_type] => utility [patent_app_number] => 10/830244 [patent_app_country] => US [patent_app_date] => 2004-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6208 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/555/07555634.pdf [firstpage_image] =>[orig_patent_app_number] => 10830244 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/830244
Multiple data hazards detection and resolution unit Apr 21, 2004 Issued
Array ( [id] => 659370 [patent_doc_number] => 07111150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Data processor' [patent_app_type] => utility [patent_app_number] => 10/824260 [patent_app_country] => US [patent_app_date] => 2004-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 16522 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111150.pdf [firstpage_image] =>[orig_patent_app_number] => 10824260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/824260
Data processor Apr 12, 2004 Issued
Array ( [id] => 7021574 [patent_doc_number] => 20050223199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Method and system to provide user-level multithreading' [patent_app_type] => utility [patent_app_number] => 10/816103 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12320 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20050223199.pdf [firstpage_image] =>[orig_patent_app_number] => 10816103 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/816103
Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution Mar 30, 2004 Issued
Array ( [id] => 864066 [patent_doc_number] => 07373490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Emptying packed data state during execution of packed data instructions' [patent_app_type] => utility [patent_app_number] => 10/805609 [patent_app_country] => US [patent_app_date] => 2004-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 32323 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/373/07373490.pdf [firstpage_image] =>[orig_patent_app_number] => 10805609 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/805609
Emptying packed data state during execution of packed data instructions Mar 18, 2004 Issued
Array ( [id] => 332970 [patent_doc_number] => 07512771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unit' [patent_app_type] => utility [patent_app_number] => 10/780083 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10118 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512771.pdf [firstpage_image] =>[orig_patent_app_number] => 10780083 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/780083
Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unit Feb 16, 2004 Issued
Array ( [id] => 7140620 [patent_doc_number] => 20050182915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Chip multiprocessor for media applications' [patent_app_type] => utility [patent_app_number] => 10/777934 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20050182915.pdf [firstpage_image] =>[orig_patent_app_number] => 10777934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/777934
Chip multiprocessor for media applications Feb 11, 2004 Abandoned
Array ( [id] => 536422 [patent_doc_number] => 07191320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Apparatus and method for performing a detached load operation in a pipeline microprocessor' [patent_app_type] => utility [patent_app_number] => 10/776751 [patent_app_country] => US [patent_app_date] => 2004-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7112 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191320.pdf [firstpage_image] =>[orig_patent_app_number] => 10776751 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776751
Apparatus and method for performing a detached load operation in a pipeline microprocessor Feb 10, 2004 Issued
Array ( [id] => 465931 [patent_doc_number] => 07243213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product' [patent_app_type] => utility [patent_app_number] => 10/776024 [patent_app_country] => US [patent_app_date] => 2004-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 19354 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243213.pdf [firstpage_image] =>[orig_patent_app_number] => 10776024 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776024
Process for translating instructions for an arm-type processor into instructions for a LX-type processor; relative translator device and computer program product Feb 9, 2004 Issued
Array ( [id] => 6913945 [patent_doc_number] => 20050177703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Thread ID in a multithreaded processor' [patent_app_type] => utility [patent_app_number] => 10/774226 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3900 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20050177703.pdf [firstpage_image] =>[orig_patent_app_number] => 10774226 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/774226
Thread ID in a multithreaded processor Feb 5, 2004 Issued
Array ( [id] => 599968 [patent_doc_number] => 07441101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-21 [patent_title] => 'Thread-aware instruction fetching in a multithreaded embedded processor' [patent_app_type] => utility [patent_app_number] => 10/773385 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8545 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/441/07441101.pdf [firstpage_image] =>[orig_patent_app_number] => 10773385 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/773385
Thread-aware instruction fetching in a multithreaded embedded processor Feb 4, 2004 Issued
Array ( [id] => 548890 [patent_doc_number] => 07185182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Pipelined microprocessor, apparatus, and method for generating early instruction results' [patent_app_type] => utility [patent_app_number] => 10/771630 [patent_app_country] => US [patent_app_date] => 2004-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185182.pdf [firstpage_image] =>[orig_patent_app_number] => 10771630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/771630
Pipelined microprocessor, apparatus, and method for generating early instruction results Feb 3, 2004 Issued
Array ( [id] => 485713 [patent_doc_number] => 07225319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Digital architecture for reconfigurable computing in digital signal processing' [patent_app_type] => utility [patent_app_number] => 10/770122 [patent_app_country] => US [patent_app_date] => 2004-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3842 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/225/07225319.pdf [firstpage_image] =>[orig_patent_app_number] => 10770122 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/770122
Digital architecture for reconfigurable computing in digital signal processing Feb 1, 2004 Issued
Array ( [id] => 7161112 [patent_doc_number] => 20050028159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Memory managing system and task controller in multitask system' [patent_app_type] => utility [patent_app_number] => 10/766952 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5751 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20050028159.pdf [firstpage_image] =>[orig_patent_app_number] => 10766952 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766952
Memory managing system and task controller in multitask system Jan 29, 2004 Abandoned
Array ( [id] => 7436405 [patent_doc_number] => 20040230771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Reconfigurable signal processing IC with an embedded flash memory device' [patent_app_type] => new [patent_app_number] => 10/768401 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2688 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230771.pdf [firstpage_image] =>[orig_patent_app_number] => 10768401 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/768401
Reconfigurable signal processing IC with an embedded flash memory device Jan 29, 2004 Issued
Array ( [id] => 623296 [patent_doc_number] => 07143270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'System and method for adding an instruction to an instruction set architecture' [patent_app_type] => utility [patent_app_number] => 10/769203 [patent_app_country] => US [patent_app_date] => 2004-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5676 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143270.pdf [firstpage_image] =>[orig_patent_app_number] => 10769203 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/769203
System and method for adding an instruction to an instruction set architecture Jan 29, 2004 Issued
Array ( [id] => 7358699 [patent_doc_number] => 20040250051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Predication instruction within a data processing system' [patent_app_type] => new [patent_app_number] => 10/765867 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5934 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20040250051.pdf [firstpage_image] =>[orig_patent_app_number] => 10765867 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/765867
Predication instruction within a data processing system Jan 28, 2004 Issued
Array ( [id] => 534583 [patent_doc_number] => 07194598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'System and method using embedded microprocessor as a node in an adaptable computing machine' [patent_app_type] => utility [patent_app_number] => 10/765556 [patent_app_country] => US [patent_app_date] => 2004-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 13085 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194598.pdf [firstpage_image] =>[orig_patent_app_number] => 10765556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/765556
System and method using embedded microprocessor as a node in an adaptable computing machine Jan 25, 2004 Issued
Array ( [id] => 7206808 [patent_doc_number] => 20050166037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Method of avoiding flush due to store queue full in a high frequency system with a stall mechanism and no reject mechanism' [patent_app_type] => utility [patent_app_number] => 10/763089 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3642 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20050166037.pdf [firstpage_image] =>[orig_patent_app_number] => 10763089 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/763089
Method of avoiding flush due to store queue full in a high frequency system with a stall mechanism and no reject mechanism Jan 21, 2004 Issued
Array ( [id] => 582323 [patent_doc_number] => 07162612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-09 [patent_title] => 'Mechanism in a microprocessor for executing native instructions directly from memory' [patent_app_type] => utility [patent_app_number] => 10/761845 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11932 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/162/07162612.pdf [firstpage_image] =>[orig_patent_app_number] => 10761845 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761845
Mechanism in a microprocessor for executing native instructions directly from memory Jan 20, 2004 Issued
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