Eliseo Ramos Feliciano

Array ( [id] => 590180 [patent_doc_number] => 07464252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Programmable processor and system for partitioned floating-point multiply-add operation' [patent_app_type] => utility [patent_app_number] => 10/757836 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 152 [patent_figures_cnt] => 136 [patent_no_of_words] => 24703 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464252.pdf [firstpage_image] =>[orig_patent_app_number] => 10757836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 175589 [patent_doc_number] => 07660972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Method and software for partitioned floating-point multiply-add operation' [patent_app_type] => utility [patent_app_number] => 10/757851 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 156 [patent_figures_cnt] => 140 [patent_no_of_words] => 24853 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/660/07660972.pdf [firstpage_image] =>[orig_patent_app_number] => 10757851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 272275 [patent_doc_number] => 07565515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Method and software for store multiplex operation' [patent_app_type] => utility [patent_app_number] => 10/757866 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 151 [patent_figures_cnt] => 138 [patent_no_of_words] => 24692 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/565/07565515.pdf [firstpage_image] =>[orig_patent_app_number] => 10757866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 503841 [patent_doc_number] => 07213131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Programmable processor and method for partitioned group element selection operation' [patent_app_type] => utility [patent_app_number] => 10/757524 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 152 [patent_figures_cnt] => 137 [patent_no_of_words] => 24758 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/213/07213131.pdf [firstpage_image] =>[orig_patent_app_number] => 10757524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7300405 [patent_doc_number] => 20040215942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method and software for multithreaded processor with partitioned operations' [patent_app_type] => new [patent_app_number] => 10/757515 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 153 [patent_figures_cnt] => 153 [patent_no_of_words] => 24807 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215942.pdf [firstpage_image] =>[orig_patent_app_number] => 10757515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 316897 [patent_doc_number] => 07526635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Programmable processor and system for store multiplex operation' [patent_app_type] => utility [patent_app_number] => 10/757516 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 152 [patent_figures_cnt] => 137 [patent_no_of_words] => 24758 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/526/07526635.pdf [firstpage_image] =>[orig_patent_app_number] => 10757516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 548804 [patent_doc_number] => 07185175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Configurable bi-directional bus for communicating between autonomous units' [patent_app_type] => utility [patent_app_number] => 10/757673 [patent_app_country] => US [patent_app_date] => 2004-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 9126 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185175.pdf [firstpage_image] =>[orig_patent_app_number] => 10757673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7299582 [patent_doc_number] => 20040215593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data' [patent_app_type] => new [patent_app_number] => 10/755188 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 17869 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215593.pdf [firstpage_image] =>[orig_patent_app_number] => 10755188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7246582 [patent_doc_number] => 20040158692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Microcontroller instruction set' [patent_app_type] => new [patent_app_number] => 10/751210 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 96 [patent_figures_cnt] => 96 [patent_no_of_words] => 12306 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20040158692.pdf [firstpage_image] =>[orig_patent_app_number] => 10751210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 343151 [patent_doc_number] => 07502912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Method and apparatus for rescheduling operations in a processor' [patent_app_type] => utility [patent_app_number] => 10/749272 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3444 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502912.pdf [firstpage_image] =>[orig_patent_app_number] => 10749272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 900131 [patent_doc_number] => 07343477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-11 [patent_title] => 'Efficient read after write bypass' [patent_app_type] => utility [patent_app_number] => 10/747584 [patent_app_country] => US [patent_app_date] => 2003-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5983 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/343/07343477.pdf [firstpage_image] =>[orig_patent_app_number] => 10747584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7100242 [patent_doc_number] => 20050132107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Fast, scalable pattern-matching engine' [patent_app_type] => utility [patent_app_number] => 10/733343 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3760 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132107.pdf [firstpage_image] =>[orig_patent_app_number] => 10733343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 513128 [patent_doc_number] => 07206923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Method and apparatus for eliminating the need for register assignment, allocation, spilling and re-filling' [patent_app_type] => utility [patent_app_number] => 10/735054 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4419 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206923.pdf [firstpage_image] =>[orig_patent_app_number] => 10735054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 904910 [patent_doc_number] => 07340590 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Handling register dependencies between instructions specifying different width registers' [patent_app_type] => utility [patent_app_number] => 10/734763 [patent_app_country] => US [patent_app_date] => 2003-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5325 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340590.pdf [firstpage_image] =>[orig_patent_app_number] => 10734763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7474276 [patent_doc_number] => 20040168062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Contents transmission/reception scheme with function for limiting recipients' [patent_app_type] => new [patent_app_number] => 10/729964 [patent_app_country] => US [patent_app_date] => 2003-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14671 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20040168062.pdf [firstpage_image] =>[orig_patent_app_number] => 10729964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 453393 [patent_doc_number] => 07251720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Flexible digital signal processor' [patent_app_type] => utility [patent_app_number] => 10/729023 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6066 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/251/07251720.pdf [firstpage_image] =>[orig_patent_app_number] => 10729023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 490287 [patent_doc_number] => 07222225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Programmable processor and method for matched aligned and unaligned storage instructions' [patent_app_type] => utility [patent_app_number] => 10/716561 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 152 [patent_figures_cnt] => 137 [patent_no_of_words] => 24792 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/222/07222225.pdf [firstpage_image] =>[orig_patent_app_number] => 10716561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7246554 [patent_doc_number] => 20040158689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'System and software for matched aligned and unaligned storage instructions' [patent_app_type] => new [patent_app_number] => 10/716568 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 153 [patent_figures_cnt] => 153 [patent_no_of_words] => 24879 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20040158689.pdf [firstpage_image] =>[orig_patent_app_number] => 10716568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7476988 [patent_doc_number] => 20040098567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'System and software for catenated group shift instruction' [patent_app_type] => new [patent_app_number] => 10/712430 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 153 [patent_figures_cnt] => 153 [patent_no_of_words] => 24925 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20040098567.pdf [firstpage_image] =>[orig_patent_app_number] => 10712430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 444389 [patent_doc_number] => 07260708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Programmable processor and method for partitioned group shift' [patent_app_type] => utility [patent_app_number] => 10/705946 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 152 [patent_figures_cnt] => 136 [patent_no_of_words] => 24709 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/260/07260708.pdf [firstpage_image] =>[orig_patent_app_number] => 10705946 [rel_patent_id] =>[rel_patent_doc_number] =>)