
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7462729
[patent_doc_number] => 20040095355
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[patent_kind] => A1
[patent_issue_date] => 2004-05-20
[patent_title] => 'Computer chipsets having data reordering mechanism'
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[patent_app_number] => 10/712843
[patent_app_country] => US
[patent_app_date] => 2003-11-12
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[pdf_file] => publications/A1/0095/20040095355.pdf
[firstpage_image] =>[orig_patent_app_number] => 10712843
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Array
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[patent_issue_date] => 2004-06-24
[patent_title] => 'Method and apparatus for managing access to out-of-frame registers'
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Array
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[patent_title] => 'Method and apparatus for managing access to out-of-frame registers'
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Array
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[patent_issue_date] => 2004-05-20
[patent_title] => 'Multi-processor system and method of accessing data therein'
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Array
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[patent_title] => 'Methods and apparatus for establishing port priority functions in a VLIW processor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/695071 | Methods and apparatus for establishing port priority functions in a VLIW processor | Oct 27, 2003 | Issued |
Array
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[patent_title] => 'System and method for executing hybridized code on a dynamically configurable hardware environment'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/694282 | System and method for executing hybridized code on a dynamically configurable hardware environment | Oct 26, 2003 | Issued |
Array
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[patent_title] => 'Staggering execution of a single packed data instruction using the same circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/689291 | Staggering execution of a single packed data instruction using the same circuit | Oct 19, 2003 | Issued |
Array
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[patent_title] => 'Processor which accelerates execution of binary programs intended for execution on a conventional processor core, using a reconfigurable combinational logic array, a function lookup unit, and a compatible conventional processor core, without requiring recompilation'
[patent_app_type] => utility
[patent_app_number] => 10/681404
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Array
(
[id] => 137220
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[patent_title] => 'System and method of instruction modification'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/672790 | System and method of instruction modification | Sep 25, 2003 | Issued |
Array
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Array
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Array
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Array
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Array
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Array
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