Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7462729 [patent_doc_number] => 20040095355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Computer chipsets having data reordering mechanism' [patent_app_type] => new [patent_app_number] => 10/712843 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4881 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20040095355.pdf [firstpage_image] =>[orig_patent_app_number] => 10712843 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712843
Computer chipsets having data reordering mechanism Nov 11, 2003 Abandoned
Array ( [id] => 7476934 [patent_doc_number] => 20040123083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Method and apparatus for managing access to out-of-frame registers' [patent_app_type] => new [patent_app_number] => 10/702252 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9513 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20040123083.pdf [firstpage_image] =>[orig_patent_app_number] => 10702252 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/702252
Method and apparatus for managing access to out-of-frame registers Nov 5, 2003 Issued
Array ( [id] => 7373987 [patent_doc_number] => 20040093486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Method and apparatus for managing access to out-of-frame registers' [patent_app_type] => new [patent_app_number] => 10/702355 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9524 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20040093486.pdf [firstpage_image] =>[orig_patent_app_number] => 10702355 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/702355
Method and apparatus for managing access to out-of-frame registers Nov 5, 2003 Issued
Array ( [id] => 7476981 [patent_doc_number] => 20040098561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Multi-processor system and method of accessing data therein' [patent_app_type] => new [patent_app_number] => 10/696146 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20040098561.pdf [firstpage_image] =>[orig_patent_app_number] => 10696146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696146
Multi-processor system and method of accessing data therein Oct 28, 2003 Abandoned
Array ( [id] => 757700 [patent_doc_number] => 07024540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Methods and apparatus for establishing port priority functions in a VLIW processor' [patent_app_type] => utility [patent_app_number] => 10/695071 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6606 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024540.pdf [firstpage_image] =>[orig_patent_app_number] => 10695071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695071
Methods and apparatus for establishing port priority functions in a VLIW processor Oct 27, 2003 Issued
Array ( [id] => 749443 [patent_doc_number] => 07032103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'System and method for executing hybridized code on a dynamically configurable hardware environment' [patent_app_type] => utility [patent_app_number] => 10/694282 [patent_app_country] => US [patent_app_date] => 2003-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 8659 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032103.pdf [firstpage_image] =>[orig_patent_app_number] => 10694282 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/694282
System and method for executing hybridized code on a dynamically configurable hardware environment Oct 26, 2003 Issued
Array ( [id] => 987745 [patent_doc_number] => 06925553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Staggering execution of a single packed data instruction using the same circuit' [patent_app_type] => utility [patent_app_number] => 10/689291 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6683 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/925/06925553.pdf [firstpage_image] =>[orig_patent_app_number] => 10689291 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/689291
Staggering execution of a single packed data instruction using the same circuit Oct 19, 2003 Issued
Array ( [id] => 653616 [patent_doc_number] => 07114062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Processor which accelerates execution of binary programs intended for execution on a conventional processor core, using a reconfigurable combinational logic array, a function lookup unit, and a compatible conventional processor core, without requiring recompilation' [patent_app_type] => utility [patent_app_number] => 10/681404 [patent_app_country] => US [patent_app_date] => 2003-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5559 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/114/07114062.pdf [firstpage_image] =>[orig_patent_app_number] => 10681404 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/681404
Processor which accelerates execution of binary programs intended for execution on a conventional processor core, using a reconfigurable combinational logic array, a function lookup unit, and a compatible conventional processor core, without requiring recompilation Oct 7, 2003 Issued
Array ( [id] => 137220 [patent_doc_number] => 07698539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-13 [patent_title] => 'System and method of instruction modification' [patent_app_type] => utility [patent_app_number] => 10/672790 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6183 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698539.pdf [firstpage_image] =>[orig_patent_app_number] => 10672790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/672790
System and method of instruction modification Sep 25, 2003 Issued
Array ( [id] => 7360723 [patent_doc_number] => 20040049659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Data processing device' [patent_app_type] => new [patent_app_number] => 10/654927 [patent_app_country] => US [patent_app_date] => 2003-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8047 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20040049659.pdf [firstpage_image] =>[orig_patent_app_number] => 10654927 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654927
Data processing device Sep 4, 2003 Issued
Array ( [id] => 999075 [patent_doc_number] => 06915409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-05 [patent_title] => 'Computerized information retrieval system' [patent_app_type] => utility [patent_app_number] => 10/646540 [patent_app_country] => US [patent_app_date] => 2003-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 10736 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915409.pdf [firstpage_image] =>[orig_patent_app_number] => 10646540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/646540
Computerized information retrieval system Aug 21, 2003 Issued
Array ( [id] => 444385 [patent_doc_number] => 07260706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Branch misprediction recovery using a side memory' [patent_app_type] => utility [patent_app_number] => 10/642586 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/260/07260706.pdf [firstpage_image] =>[orig_patent_app_number] => 10642586 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/642586
Branch misprediction recovery using a side memory Aug 18, 2003 Issued
Array ( [id] => 536443 [patent_doc_number] => 07191321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Microengine for parallel processor architecture' [patent_app_type] => utility [patent_app_number] => 10/643438 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11026 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191321.pdf [firstpage_image] =>[orig_patent_app_number] => 10643438 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/643438
Microengine for parallel processor architecture Aug 18, 2003 Issued
Array ( [id] => 816506 [patent_doc_number] => 07415598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Message synchronization in network processors' [patent_app_type] => utility [patent_app_number] => 10/640883 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4007 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/415/07415598.pdf [firstpage_image] =>[orig_patent_app_number] => 10640883 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/640883
Message synchronization in network processors Aug 12, 2003 Issued
Array ( [id] => 5633536 [patent_doc_number] => 20060150007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Parallel processing platform with synchronous system halt/resume' [patent_app_type] => utility [patent_app_number] => 10/524501 [patent_app_country] => US [patent_app_date] => 2003-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3915 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20060150007.pdf [firstpage_image] =>[orig_patent_app_number] => 10524501 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/524501
Parallel processing platform with synchronous system halt/resume Aug 11, 2003 Abandoned
Array ( [id] => 7393962 [patent_doc_number] => 20040030867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Processing system and method for efficiently enabling detection of data hazards for long latency instructions' [patent_app_type] => new [patent_app_number] => 10/636073 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7307 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20040030867.pdf [firstpage_image] =>[orig_patent_app_number] => 10636073 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/636073
Processing system and method for efficiently enabling detection of data hazards for long latency instructions Aug 6, 2003 Issued
Array ( [id] => 7675942 [patent_doc_number] => 20040153885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Test and skip processor instruction having at least one register operand' [patent_app_type] => new [patent_app_number] => 10/632084 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5078 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153885.pdf [firstpage_image] =>[orig_patent_app_number] => 10632084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632084
Test and skip processor instruction having at least one register operand Jul 30, 2003 Issued
Array ( [id] => 503893 [patent_doc_number] => 07213136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Apparatus and method for redundant zero micro-operation removal' [patent_app_type] => utility [patent_app_number] => 10/631628 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5367 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/213/07213136.pdf [firstpage_image] =>[orig_patent_app_number] => 10631628 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631628
Apparatus and method for redundant zero micro-operation removal Jul 29, 2003 Issued
Array ( [id] => 7160318 [patent_doc_number] => 20050027967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Apparatus and method for two micro-operation flow using source override' [patent_app_type] => utility [patent_app_number] => 10/631629 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5952 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20050027967.pdf [firstpage_image] =>[orig_patent_app_number] => 10631629 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631629
Apparatus and method for two micro-operation flow using source override Jul 29, 2003 Issued
Array ( [id] => 7352943 [patent_doc_number] => 20040193842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Active memory processing array topography and method' [patent_app_type] => new [patent_app_number] => 10/629382 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4002 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193842.pdf [firstpage_image] =>[orig_patent_app_number] => 10629382 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/629382
Active memory processing array topography and method Jul 27, 2003 Issued
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