Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 615779 [patent_doc_number] => 07149875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Data reordering processor and method for use in an active memory device' [patent_app_type] => utility [patent_app_number] => 10/629378 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5776 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149875.pdf [firstpage_image] =>[orig_patent_app_number] => 10629378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/629378
Data reordering processor and method for use in an active memory device Jul 27, 2003 Issued
Array ( [id] => 653614 [patent_doc_number] => 07114061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Information processing apparatus with configurable processor' [patent_app_type] => utility [patent_app_number] => 10/627709 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 6886 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/114/07114061.pdf [firstpage_image] =>[orig_patent_app_number] => 10627709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/627709
Information processing apparatus with configurable processor Jul 27, 2003 Issued
Array ( [id] => 7676342 [patent_doc_number] => 20040153485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Arithmetic apparatus and arithmetic method' [patent_app_type] => new [patent_app_number] => 10/625871 [patent_app_country] => US [patent_app_date] => 2003-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4460 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153485.pdf [firstpage_image] =>[orig_patent_app_number] => 10625871 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/625871
Arithmetic apparatus and arithmetic method Jul 23, 2003 Issued
Array ( [id] => 7373945 [patent_doc_number] => 20040093479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Cache for instruction set architecture using indexes to achieve compression' [patent_app_type] => new [patent_app_number] => 10/628083 [patent_app_country] => US [patent_app_date] => 2003-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20040093479.pdf [firstpage_image] =>[orig_patent_app_number] => 10628083 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/628083
Cache for instruction set architecture using indexes to achieve compression Jul 23, 2003 Issued
Array ( [id] => 458015 [patent_doc_number] => 07249242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Input pipeline registers for a node in an adaptive computing engine' [patent_app_type] => utility [patent_app_number] => 10/626479 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7208 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/249/07249242.pdf [firstpage_image] =>[orig_patent_app_number] => 10626479 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/626479
Input pipeline registers for a node in an adaptive computing engine Jul 22, 2003 Issued
Array ( [id] => 1007707 [patent_doc_number] => 06907518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same' [patent_app_type] => utility [patent_app_number] => 10/462585 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/907/06907518.pdf [firstpage_image] =>[orig_patent_app_number] => 10462585 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462585
Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same Jun 15, 2003 Issued
Array ( [id] => 7445366 [patent_doc_number] => 20040003204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Hardware accelerator for a platform-independent code' [patent_app_type] => new [patent_app_number] => 10/457409 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5484 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003204.pdf [firstpage_image] =>[orig_patent_app_number] => 10457409 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/457409
Hardware accelerator for a platform-independent code Jun 9, 2003 Issued
Array ( [id] => 472871 [patent_doc_number] => 07234041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-19 [patent_title] => 'Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems' [patent_app_type] => utility [patent_app_number] => 10/458470 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2619 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/234/07234041.pdf [firstpage_image] =>[orig_patent_app_number] => 10458470 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/458470
Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems Jun 9, 2003 Issued
Array ( [id] => 562460 [patent_doc_number] => 07165167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Load store unit with replay mechanism' [patent_app_type] => utility [patent_app_number] => 10/458457 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8597 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/165/07165167.pdf [firstpage_image] =>[orig_patent_app_number] => 10458457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/458457
Load store unit with replay mechanism Jun 9, 2003 Issued
Array ( [id] => 7358694 [patent_doc_number] => 20040250050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Method and apparatus for controlling program instruction completion timing for processor verification' [patent_app_type] => new [patent_app_number] => 10/457610 [patent_app_country] => US [patent_app_date] => 2003-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20040250050.pdf [firstpage_image] =>[orig_patent_app_number] => 10457610 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/457610
Method and apparatus for controlling program instruction completion timing for processor verification Jun 8, 2003 Issued
Array ( [id] => 7358708 [patent_doc_number] => 20040250054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Line prediction using return prediction information' [patent_app_type] => new [patent_app_number] => 10/458333 [patent_app_country] => US [patent_app_date] => 2003-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7910 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20040250054.pdf [firstpage_image] =>[orig_patent_app_number] => 10458333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/458333
Line prediction using return prediction information Jun 8, 2003 Abandoned
Array ( [id] => 7174300 [patent_doc_number] => 20040078554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Digital signal processor with cascaded SIMD organization' [patent_app_type] => new [patent_app_number] => 10/456793 [patent_app_country] => US [patent_app_date] => 2003-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7939 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078554.pdf [firstpage_image] =>[orig_patent_app_number] => 10456793 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/456793
Digital signal processor with cascaded SIMD organization Jun 6, 2003 Issued
Array ( [id] => 7474206 [patent_doc_number] => 20040168046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Instruction rollback processor system, an instruction rollback method and an instruction rollback program' [patent_app_type] => new [patent_app_number] => 10/449082 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9421 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20040168046.pdf [firstpage_image] =>[orig_patent_app_number] => 10449082 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449082
Instruction rollback processor system, an instruction rollback method and an instruction rollback program Jun 1, 2003 Issued
Array ( [id] => 548817 [patent_doc_number] => 07185176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Processor executing SIMD instructions' [patent_app_type] => utility [patent_app_number] => 10/449788 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 741 [patent_figures_cnt] => 749 [patent_no_of_words] => 24116 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185176.pdf [firstpage_image] =>[orig_patent_app_number] => 10449788 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449788
Processor executing SIMD instructions Jun 1, 2003 Issued
Array ( [id] => 7459887 [patent_doc_number] => 20040100900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Message transfer system' [patent_app_type] => new [patent_app_number] => 10/452782 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7776 [patent_no_of_claims] => 89 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20040100900.pdf [firstpage_image] =>[orig_patent_app_number] => 10452782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452782
Message transfer system May 29, 2003 Abandoned
Array ( [id] => 581944 [patent_doc_number] => 07159101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-02 [patent_title] => 'System and method to trace high performance multi-issue processors' [patent_app_type] => utility [patent_app_number] => 10/448324 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7770 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/159/07159101.pdf [firstpage_image] =>[orig_patent_app_number] => 10448324 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448324
System and method to trace high performance multi-issue processors May 27, 2003 Issued
Array ( [id] => 329500 [patent_doc_number] => 07516308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Processor for performing group floating-point operations' [patent_app_type] => utility [patent_app_number] => 10/436340 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 101 [patent_figures_cnt] => 95 [patent_no_of_words] => 18552 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516308.pdf [firstpage_image] =>[orig_patent_app_number] => 10436340 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436340
Processor for performing group floating-point operations May 12, 2003 Issued
Array ( [id] => 5728714 [patent_doc_number] => 20060059475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Control word hoisting' [patent_app_type] => utility [patent_app_number] => 10/515162 [patent_app_country] => US [patent_app_date] => 2003-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4887 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20060059475.pdf [firstpage_image] =>[orig_patent_app_number] => 10515162 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/515162
Control word hoisting Apr 24, 2003 Abandoned
Array ( [id] => 7282142 [patent_doc_number] => 20040064519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Controller with fail-safe function' [patent_app_type] => new [patent_app_number] => 10/408749 [patent_app_country] => US [patent_app_date] => 2003-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5987 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20040064519.pdf [firstpage_image] =>[orig_patent_app_number] => 10408749 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/408749
Controller with fail-safe function Apr 6, 2003 Issued
Array ( [id] => 6866401 [patent_doc_number] => 20030191927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Multiple-thread processor with in-pipeline, thread selectable storage' [patent_app_type] => new [patent_app_number] => 10/403406 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18457 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20030191927.pdf [firstpage_image] =>[orig_patent_app_number] => 10403406 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/403406
Multiple-thread processor with in-pipeline, thread selectable storage Mar 30, 2003 Issued
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