Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6836133 [patent_doc_number] => 20030163679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Method and apparatus for loop buffering digital signal processing instructions' [patent_app_type] => new [patent_app_number] => 10/356825 [patent_app_country] => US [patent_app_date] => 2003-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10424 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163679.pdf [firstpage_image] =>[orig_patent_app_number] => 10356825 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/356825
Method and apparatus for loop buffering digital signal processing instructions Feb 2, 2003 Issued
Array ( [id] => 1234354 [patent_doc_number] => 06697937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Split history tables for branch prediction' [patent_app_type] => B1 [patent_app_number] => 10/353203 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10472 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697937.pdf [firstpage_image] =>[orig_patent_app_number] => 10353203 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353203
Split history tables for branch prediction Jan 27, 2003 Issued
Array ( [id] => 6661071 [patent_doc_number] => 20030135715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Enhanced virtual renaming scheme and deadlock prevention therefor' [patent_app_type] => new [patent_app_number] => 10/351444 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4907 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135715.pdf [firstpage_image] =>[orig_patent_app_number] => 10351444 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/351444
Enhanced virtual renaming scheme and deadlock prevention therefor Jan 26, 2003 Issued
Array ( [id] => 637523 [patent_doc_number] => 07130987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Reconfigurable semantic processor' [patent_app_type] => utility [patent_app_number] => 10/351030 [patent_app_country] => US [patent_app_date] => 2003-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9703 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/130/07130987.pdf [firstpage_image] =>[orig_patent_app_number] => 10351030 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/351030
Reconfigurable semantic processor Jan 23, 2003 Issued
Array ( [id] => 953335 [patent_doc_number] => 06961841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem' [patent_app_type] => utility [patent_app_number] => 10/339133 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3454 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/961/06961841.pdf [firstpage_image] =>[orig_patent_app_number] => 10339133 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339133
Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem Jan 7, 2003 Issued
Array ( [id] => 1170130 [patent_doc_number] => 06766439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Apparatus and method for dynamic program decompression' [patent_app_type] => B2 [patent_app_number] => 10/328525 [patent_app_country] => US [patent_app_date] => 2002-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4952 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766439.pdf [firstpage_image] =>[orig_patent_app_number] => 10328525 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328525
Apparatus and method for dynamic program decompression Dec 23, 2002 Issued
Array ( [id] => 6707628 [patent_doc_number] => 20030154362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Method and system for safe data dependency collapsing based on control-flow speculation' [patent_app_type] => new [patent_app_number] => 10/307557 [patent_app_country] => US [patent_app_date] => 2002-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9024 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20030154362.pdf [firstpage_image] =>[orig_patent_app_number] => 10307557 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/307557
Method and system for safe data dependency collapsing based on control-flow speculation Dec 1, 2002 Issued
Array ( [id] => 1243156 [patent_doc_number] => 06684318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-27 [patent_title] => 'Intermediate-grain reconfigurable processing device' [patent_app_type] => B2 [patent_app_number] => 10/293887 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 38 [patent_no_of_words] => 15332 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684318.pdf [firstpage_image] =>[orig_patent_app_number] => 10293887 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/293887
Intermediate-grain reconfigurable processing device Nov 11, 2002 Issued
Array ( [id] => 485742 [patent_doc_number] => 07225324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions' [patent_app_type] => utility [patent_app_number] => 10/285318 [patent_app_country] => US [patent_app_date] => 2002-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 6585 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/225/07225324.pdf [firstpage_image] =>[orig_patent_app_number] => 10285318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/285318
Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions Oct 30, 2002 Issued
Array ( [id] => 599988 [patent_doc_number] => 07441111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Controlled program execution by a portable data carrier' [patent_app_type] => utility [patent_app_number] => 10/495569 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4350 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/441/07441111.pdf [firstpage_image] =>[orig_patent_app_number] => 10495569 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/495569
Controlled program execution by a portable data carrier Oct 28, 2002 Issued
Array ( [id] => 1201035 [patent_doc_number] => 06728868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'System and method for coalescing data utilized to detect data hazards' [patent_app_type] => B2 [patent_app_number] => 10/282183 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 15419 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728868.pdf [firstpage_image] =>[orig_patent_app_number] => 10282183 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282183
System and method for coalescing data utilized to detect data hazards Oct 27, 2002 Issued
Array ( [id] => 1177671 [patent_doc_number] => 06760832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Data processor' [patent_app_type] => B2 [patent_app_number] => 10/281148 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8076 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760832.pdf [firstpage_image] =>[orig_patent_app_number] => 10281148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/281148
Data processor Oct 27, 2002 Issued
Array ( [id] => 6784457 [patent_doc_number] => 20030065905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Parallel computation processor, parallel computation control method and program thereof' [patent_app_type] => new [patent_app_number] => 10/254543 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4445 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065905.pdf [firstpage_image] =>[orig_patent_app_number] => 10254543 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254543
Parallel computation processor, parallel computation control method and program thereof Sep 25, 2002 Issued
Array ( [id] => 937576 [patent_doc_number] => 06976153 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Floating point unit with try-again reservation station and method of operation' [patent_app_type] => utility [patent_app_number] => 10/254022 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3248 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/976/06976153.pdf [firstpage_image] =>[orig_patent_app_number] => 10254022 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254022
Floating point unit with try-again reservation station and method of operation Sep 23, 2002 Issued
Array ( [id] => 7631543 [patent_doc_number] => 06665794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Data reordering mechanism for data transfer in computer systems' [patent_app_type] => B2 [patent_app_number] => 10/254146 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4793 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665794.pdf [firstpage_image] =>[orig_patent_app_number] => 10254146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254146
Data reordering mechanism for data transfer in computer systems Sep 23, 2002 Issued
Array ( [id] => 465939 [patent_doc_number] => 07243217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-10 [patent_title] => 'Floating point unit with variable speed execution pipeline and method of operation' [patent_app_type] => utility [patent_app_number] => 10/254084 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 2 [patent_no_of_words] => 2721 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243217.pdf [firstpage_image] =>[orig_patent_app_number] => 10254084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254084
Floating point unit with variable speed execution pipeline and method of operation Sep 23, 2002 Issued
Array ( [id] => 7621140 [patent_doc_number] => 06978361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Effectively infinite branch prediction table mechanism' [patent_app_type] => utility [patent_app_number] => 10/251047 [patent_app_country] => US [patent_app_date] => 2002-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2374 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/978/06978361.pdf [firstpage_image] =>[orig_patent_app_number] => 10251047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/251047
Effectively infinite branch prediction table mechanism Sep 19, 2002 Issued
Array ( [id] => 6722398 [patent_doc_number] => 20030056088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Processor, compiler and compilation method' [patent_app_type] => new [patent_app_number] => 10/246482 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 15718 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20030056088.pdf [firstpage_image] =>[orig_patent_app_number] => 10246482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246482
Processor, compiler and compilation method Sep 18, 2002 Issued
Array ( [id] => 947677 [patent_doc_number] => 06965986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate' [patent_app_type] => utility [patent_app_number] => 10/246937 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2132 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965986.pdf [firstpage_image] =>[orig_patent_app_number] => 10246937 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246937
Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate Sep 18, 2002 Issued
Array ( [id] => 6695925 [patent_doc_number] => 20030108119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Digital signal processor for wireless baseband processing' [patent_app_type] => new [patent_app_number] => 10/246366 [patent_app_country] => US [patent_app_date] => 2002-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2638 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20030108119.pdf [firstpage_image] =>[orig_patent_app_number] => 10246366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246366
Digital signal processor for wireless baseband processing Sep 16, 2002 Issued
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