Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1075164 [patent_doc_number] => 06839832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Register file backup queue' [patent_app_type] => utility [patent_app_number] => 10/231152 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3692 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839832.pdf [firstpage_image] =>[orig_patent_app_number] => 10231152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231152
Register file backup queue Aug 29, 2002 Issued
Array ( [id] => 7672127 [patent_doc_number] => 20040181652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor' [patent_app_type] => new [patent_app_number] => 10/228929 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7476 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20040181652.pdf [firstpage_image] =>[orig_patent_app_number] => 10228929 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/228929
Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor Aug 26, 2002 Issued
Array ( [id] => 7404812 [patent_doc_number] => 20040039898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Processor system and method providing data to selected sub-units in a processor functional unit' [patent_app_type] => new [patent_app_number] => 10/224154 [patent_app_country] => US [patent_app_date] => 2002-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 18888 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20040039898.pdf [firstpage_image] =>[orig_patent_app_number] => 10224154 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224154
Processor system and method providing data to selected sub-units in a processor functional unit Aug 19, 2002 Issued
Array ( [id] => 438414 [patent_doc_number] => 07263602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Programmable pipeline fabric utilizing partially global configuration buses' [patent_app_type] => utility [patent_app_number] => 10/222645 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2977 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/263/07263602.pdf [firstpage_image] =>[orig_patent_app_number] => 10222645 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/222645
Programmable pipeline fabric utilizing partially global configuration buses Aug 15, 2002 Issued
Array ( [id] => 7393982 [patent_doc_number] => 20040030871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Branch reconfigurable systems and methods' [patent_app_type] => new [patent_app_number] => 10/214990 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7107 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20040030871.pdf [firstpage_image] =>[orig_patent_app_number] => 10214990 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/214990
Branch reconfigurable systems and methods Aug 7, 2002 Issued
Array ( [id] => 548878 [patent_doc_number] => 07185181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Apparatus and method for maintaining a floating point data segment selector' [patent_app_type] => utility [patent_app_number] => 10/212911 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 8714 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185181.pdf [firstpage_image] =>[orig_patent_app_number] => 10212911 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212911
Apparatus and method for maintaining a floating point data segment selector Aug 4, 2002 Issued
Array ( [id] => 6336014 [patent_doc_number] => 20020199092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Split history tables for branch prediction' [patent_app_type] => new [patent_app_number] => 10/195083 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10234 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20020199092.pdf [firstpage_image] =>[orig_patent_app_number] => 10195083 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/195083
Split history tables for branch prediction Jul 11, 2002 Issued
Array ( [id] => 7445437 [patent_doc_number] => 20040003211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Extending a register file utilizing stack and queue techniques' [patent_app_type] => new [patent_app_number] => 10/185200 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6548 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003211.pdf [firstpage_image] =>[orig_patent_app_number] => 10185200 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185200
Extending a register file utilizing stack and queue techniques Jun 27, 2002 Issued
Array ( [id] => 1007706 [patent_doc_number] => 06907517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Interprocessor register succession method and device therefor' [patent_app_type] => utility [patent_app_number] => 10/163505 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13342 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/907/06907517.pdf [firstpage_image] =>[orig_patent_app_number] => 10163505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163505
Interprocessor register succession method and device therefor Jun 6, 2002 Issued
Array ( [id] => 6661201 [patent_doc_number] => 20030135845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Instruction code conversion apparatus creating an instruction code including a second code converted from a first code' [patent_app_type] => new [patent_app_number] => 10/163452 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6679 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135845.pdf [firstpage_image] =>[orig_patent_app_number] => 10163452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163452
Instruction code conversion apparatus creating an instruction code including a second code converted from a first code Jun 6, 2002 Issued
Array ( [id] => 1236352 [patent_doc_number] => 06694426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Method and apparatus for staggering execution of a single packed data instruction using the same circuit' [patent_app_type] => B2 [patent_app_number] => 10/164774 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6758 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694426.pdf [firstpage_image] =>[orig_patent_app_number] => 10164774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164774
Method and apparatus for staggering execution of a single packed data instruction using the same circuit Jun 5, 2002 Issued
Array ( [id] => 6334800 [patent_doc_number] => 20020198911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Rearranging data between vector and matrix forms in a SIMD matrix processor' [patent_app_type] => new [patent_app_number] => 10/164040 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6858 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20020198911.pdf [firstpage_image] =>[orig_patent_app_number] => 10164040 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164040
Rearranging data between vector and matrix forms in a SIMD matrix processor Jun 5, 2002 Issued
Array ( [id] => 6425061 [patent_doc_number] => 20020184474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method and apparatus for staggering execution of a single packed data instruction using the same circuit' [patent_app_type] => new [patent_app_number] => 10/164976 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6819 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184474.pdf [firstpage_image] =>[orig_patent_app_number] => 10164976 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164976
Method and apparatus for staggering execution of a single packed data instruction using the same circuit Jun 5, 2002 Issued
Array ( [id] => 792703 [patent_doc_number] => 06986025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Conditional execution per lane' [patent_app_type] => utility [patent_app_number] => 10/162070 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 10724 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/986/06986025.pdf [firstpage_image] =>[orig_patent_app_number] => 10162070 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/162070
Conditional execution per lane Jun 4, 2002 Issued
Array ( [id] => 765293 [patent_doc_number] => 07017032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Setting execution conditions' [patent_app_type] => utility [patent_app_number] => 10/162071 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 10577 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/017/07017032.pdf [firstpage_image] =>[orig_patent_app_number] => 10162071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/162071
Setting execution conditions Jun 4, 2002 Issued
Array ( [id] => 975483 [patent_doc_number] => 06938151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Hybrid branch prediction using a global selection counter and a prediction method comparison table' [patent_app_type] => utility [patent_app_number] => 10/161857 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4132 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/938/06938151.pdf [firstpage_image] =>[orig_patent_app_number] => 10161857 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/161857
Hybrid branch prediction using a global selection counter and a prediction method comparison table Jun 3, 2002 Issued
Array ( [id] => 1007705 [patent_doc_number] => 06907516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Compression of program instructions using advanced sequential correlation' [patent_app_type] => utility [patent_app_number] => 10/159857 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9641 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/907/06907516.pdf [firstpage_image] =>[orig_patent_app_number] => 10159857 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159857
Compression of program instructions using advanced sequential correlation May 29, 2002 Issued
Array ( [id] => 1120047 [patent_doc_number] => 06801997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Multiple-thread processor with single-thread interface shared among threads' [patent_app_type] => B2 [patent_app_number] => 10/154076 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 18318 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801997.pdf [firstpage_image] =>[orig_patent_app_number] => 10154076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154076
Multiple-thread processor with single-thread interface shared among threads May 22, 2002 Issued
Array ( [id] => 1007704 [patent_doc_number] => 06907515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Configuration control within data processing systems' [patent_app_type] => utility [patent_app_number] => 10/152337 [patent_app_country] => US [patent_app_date] => 2002-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 11216 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/907/06907515.pdf [firstpage_image] =>[orig_patent_app_number] => 10152337 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152337
Configuration control within data processing systems May 21, 2002 Issued
Array ( [id] => 702130 [patent_doc_number] => 07073048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Cascaded microcomputer array and method' [patent_app_type] => utility [patent_app_number] => 10/144524 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10168 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/073/07073048.pdf [firstpage_image] =>[orig_patent_app_number] => 10144524 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144524
Cascaded microcomputer array and method May 12, 2002 Issued
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