Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6726414 [patent_doc_number] => 20030208726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Incremental cost calculation for fast wire length minimization' [patent_app_type] => new [patent_app_number] => 10/063624 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 869 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20030208726.pdf [firstpage_image] =>[orig_patent_app_number] => 10063624 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/063624
Incremental cost calculation for fast wire length minimization May 2, 2002 Abandoned
Array ( [id] => 6051473 [patent_doc_number] => 20020169948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Microprocessor' [patent_app_type] => new [patent_app_number] => 10/138148 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6129 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20020169948.pdf [firstpage_image] =>[orig_patent_app_number] => 10138148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/138148
Microprocessor May 2, 2002 Issued
Array ( [id] => 6265430 [patent_doc_number] => 20020188826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Unhandled operation handling in multiple instruction set systems' [patent_app_type] => new [patent_app_number] => 10/136346 [patent_app_country] => US [patent_app_date] => 2002-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12467 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188826.pdf [firstpage_image] =>[orig_patent_app_number] => 10136346 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/136346
Unhandled operation handling in multiple instruction set systems May 1, 2002 Issued
Array ( [id] => 6726049 [patent_doc_number] => 20030208361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Configuration of systems with services' [patent_app_type] => new [patent_app_number] => 10/137623 [patent_app_country] => US [patent_app_date] => 2002-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2822 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20030208361.pdf [firstpage_image] =>[orig_patent_app_number] => 10137623 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137623
Configuration of systems with services May 1, 2002 Abandoned
Array ( [id] => 6857715 [patent_doc_number] => 20030131216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Apparatus for one-cycle decompression of compressed data and methods of operation thereof' [patent_app_type] => new [patent_app_number] => 10/135575 [patent_app_country] => US [patent_app_date] => 2002-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7852 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20030131216.pdf [firstpage_image] =>[orig_patent_app_number] => 10135575 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135575
Apparatus for one-cycle decompression of compressed data and methods of operation thereof Apr 30, 2002 Issued
Array ( [id] => 6793413 [patent_doc_number] => 20030088757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Efficient high performance data operation element for use in a reconfigurable logic environment' [patent_app_type] => new [patent_app_number] => 10/135849 [patent_app_country] => US [patent_app_date] => 2002-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 4996 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088757.pdf [firstpage_image] =>[orig_patent_app_number] => 10135849 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135849
Efficient high performance data operation element for use in a reconfigurable logic environment Apr 30, 2002 Abandoned
Array ( [id] => 1070980 [patent_doc_number] => 06845442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-18 [patent_title] => 'System and method of using speculative operand sources in order to speculatively bypass load-store operations' [patent_app_type] => utility [patent_app_number] => 10/135497 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12099 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/845/06845442.pdf [firstpage_image] =>[orig_patent_app_number] => 10135497 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135497
System and method of using speculative operand sources in order to speculatively bypass load-store operations Apr 29, 2002 Issued
Array ( [id] => 6265427 [patent_doc_number] => 20020188825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Data processing using multiple instruction sets' [patent_app_type] => new [patent_app_number] => 10/134468 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11656 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188825.pdf [firstpage_image] =>[orig_patent_app_number] => 10134468 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/134468
Data processing using multiple instruction sets Apr 29, 2002 Issued
Array ( [id] => 753070 [patent_doc_number] => 07028166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'System and method for linking speculative results of load operations to register values' [patent_app_type] => utility [patent_app_number] => 10/135496 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12038 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/028/07028166.pdf [firstpage_image] =>[orig_patent_app_number] => 10135496 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135496
System and method for linking speculative results of load operations to register values Apr 29, 2002 Issued
Array ( [id] => 6839882 [patent_doc_number] => 20030037222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Method and apparatus for controlling a massively parallel processing environment' [patent_app_type] => new [patent_app_number] => 10/112118 [patent_app_country] => US [patent_app_date] => 2002-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6287 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037222.pdf [firstpage_image] =>[orig_patent_app_number] => 10112118 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/112118
Method and apparatus for controlling a massively parallel processing environment Mar 27, 2002 Issued
Array ( [id] => 9948492 [patent_doc_number] => RE045458 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2015-04-07 [patent_title] => 'Dual function system and method for shuffling packed data elements' [patent_app_type] => reissue [patent_app_number] => 10/104205 [patent_app_country] => US [patent_app_date] => 2002-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4257 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10104205 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/104205
Dual function system and method for shuffling packed data elements Mar 20, 2002 Issued
Array ( [id] => 6831481 [patent_doc_number] => 20030182539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Storing execution results of mispredicted paths in a superscalar computer processor' [patent_app_type] => new [patent_app_number] => 10/102084 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8402 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20030182539.pdf [firstpage_image] =>[orig_patent_app_number] => 10102084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/102084
Storing execution results of mispredicted paths in a superscalar computer processor Mar 19, 2002 Abandoned
Array ( [id] => 6766934 [patent_doc_number] => 20030101334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Systems and methods for integrating emulated and native code' [patent_app_type] => new [patent_app_number] => 10/100874 [patent_app_country] => US [patent_app_date] => 2002-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9929 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101334.pdf [firstpage_image] =>[orig_patent_app_number] => 10100874 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/100874
Systems and methods for integrating emulated and native code Mar 18, 2002 Issued
Array ( [id] => 6839887 [patent_doc_number] => 20030037227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Processor enabling exception handling to be set by program' [patent_app_type] => new [patent_app_number] => 10/097375 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6146 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037227.pdf [firstpage_image] =>[orig_patent_app_number] => 10097375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/097375
Processor enabling exception handling to be set by program Mar 14, 2002 Abandoned
Array ( [id] => 5861275 [patent_doc_number] => 20020124160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Register file backup queue' [patent_app_type] => new [patent_app_number] => 10/095071 [patent_app_country] => US [patent_app_date] => 2002-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3713 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124160.pdf [firstpage_image] =>[orig_patent_app_number] => 10095071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/095071
Register file backup queue Mar 11, 2002 Issued
Array ( [id] => 721740 [patent_doc_number] => 07055021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Out-of-order processor that reduces mis-speculation using a replay scoreboard' [patent_app_type] => utility [patent_app_number] => 10/096499 [patent_app_country] => US [patent_app_date] => 2002-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 12381 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/055/07055021.pdf [firstpage_image] =>[orig_patent_app_number] => 10096499 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/096499
Out-of-order processor that reduces mis-speculation using a replay scoreboard Mar 10, 2002 Issued
Array ( [id] => 6712504 [patent_doc_number] => 20030172253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Fast instruction dependency multiplexer' [patent_app_type] => new [patent_app_number] => 10/091783 [patent_app_country] => US [patent_app_date] => 2002-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3471 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20030172253.pdf [firstpage_image] =>[orig_patent_app_number] => 10091783 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/091783
Fast instruction dependency multiplexer Mar 5, 2002 Abandoned
Array ( [id] => 1017247 [patent_doc_number] => 06895497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority' [patent_app_type] => utility [patent_app_number] => 10/092714 [patent_app_country] => US [patent_app_date] => 2002-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2358 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/895/06895497.pdf [firstpage_image] =>[orig_patent_app_number] => 10092714 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092714
Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority Mar 5, 2002 Issued
Array ( [id] => 6336006 [patent_doc_number] => 20020199091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Apparatus for branch prediction based on history table' [patent_app_type] => new [patent_app_number] => 10/091147 [patent_app_country] => US [patent_app_date] => 2002-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6509 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20020199091.pdf [firstpage_image] =>[orig_patent_app_number] => 10091147 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/091147
Apparatus and method for branch prediction where data for predictions is selected from a count in a branch history table or a bias in a branch target buffer Mar 5, 2002 Issued
Array ( [id] => 6848125 [patent_doc_number] => 20030167292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Method and apparatus for performing critical tasks using speculative operations' [patent_app_type] => new [patent_app_number] => 10/092093 [patent_app_country] => US [patent_app_date] => 2002-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5176 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20030167292.pdf [firstpage_image] =>[orig_patent_app_number] => 10092093 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092093
Method and apparatus for performing critical tasks using speculative operations Mar 3, 2002 Issued
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