Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 753084 [patent_doc_number] => 07028167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Core parallel execution with different optimization characteristics to decrease dynamic execution path' [patent_app_type] => utility [patent_app_number] => 10/091084 [patent_app_country] => US [patent_app_date] => 2002-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/028/07028167.pdf [firstpage_image] =>[orig_patent_app_number] => 10091084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/091084
Core parallel execution with different optimization characteristics to decrease dynamic execution path Mar 3, 2002 Issued
Array ( [id] => 6161517 [patent_doc_number] => 20020147901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Method of handling instructions within a processor with decoupled architecture, in particular a processor for digital signal processing, and corresponding processor' [patent_app_type] => new [patent_app_number] => 10/083629 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12468 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20020147901.pdf [firstpage_image] =>[orig_patent_app_number] => 10083629 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/083629
Method of handling instructions within a processor with decoupled architecture, in particular a processor for digital signal processing, and corresponding processor Feb 25, 2002 Issued
Array ( [id] => 6836131 [patent_doc_number] => 20030163677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Efficiently calculating a branch target address' [patent_app_type] => new [patent_app_number] => 10/082144 [patent_app_country] => US [patent_app_date] => 2002-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8699 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163677.pdf [firstpage_image] =>[orig_patent_app_number] => 10082144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082144
Efficiently calculating a branch target address Feb 24, 2002 Issued
Array ( [id] => 6741650 [patent_doc_number] => 20030159019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Prediction of instructions in a data processing apparatus' [patent_app_type] => new [patent_app_number] => 10/078276 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9324 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20030159019.pdf [firstpage_image] =>[orig_patent_app_number] => 10078276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/078276
Prediction of instructions in a data processing apparatus Feb 19, 2002 Issued
Array ( [id] => 789412 [patent_doc_number] => 06988182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'Method for upgrading firmware in an electronic device' [patent_app_type] => utility [patent_app_number] => 10/075080 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5604 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/988/06988182.pdf [firstpage_image] =>[orig_patent_app_number] => 10075080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/075080
Method for upgrading firmware in an electronic device Feb 12, 2002 Issued
Array ( [id] => 7618441 [patent_doc_number] => 06944751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Register renaming to reduce bypass and increase apparent physical register size' [patent_app_type] => utility [patent_app_number] => 10/074098 [patent_app_country] => US [patent_app_date] => 2002-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2909 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944751.pdf [firstpage_image] =>[orig_patent_app_number] => 10074098 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/074098
Register renaming to reduce bypass and increase apparent physical register size Feb 10, 2002 Issued
Array ( [id] => 6655494 [patent_doc_number] => 20030105943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Mechanism for processing speclative LL and SC instructions in a pipelined processor' [patent_app_type] => new [patent_app_number] => 10/068286 [patent_app_country] => US [patent_app_date] => 2002-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8870 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20030105943.pdf [firstpage_image] =>[orig_patent_app_number] => 10068286 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/068286
Mechanism for processing speclative LL and SC instructions in a pipelined processor Feb 5, 2002 Issued
Array ( [id] => 5910556 [patent_doc_number] => 20020144092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Handling of loops in processors' [patent_app_type] => new [patent_app_number] => 10/059566 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9600 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144092.pdf [firstpage_image] =>[orig_patent_app_number] => 10059566 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/059566
Handling of loops in processors Jan 28, 2002 Abandoned
Array ( [id] => 6852970 [patent_doc_number] => 20030145173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Context pipelines' [patent_app_type] => new [patent_app_number] => 10/057723 [patent_app_country] => US [patent_app_date] => 2002-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4397 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20030145173.pdf [firstpage_image] =>[orig_patent_app_number] => 10057723 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/057723
Context pipelines Jan 24, 2002 Issued
Array ( [id] => 6020074 [patent_doc_number] => 20020103986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Data processing system, data processing apparatus and control method for a data processing apparatus' [patent_app_type] => new [patent_app_number] => 10/053737 [patent_app_country] => US [patent_app_date] => 2002-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15615 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20020103986.pdf [firstpage_image] =>[orig_patent_app_number] => 10053737 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/053737
Data processing system, data processing apparatus and control method for a data processing apparatus Jan 23, 2002 Issued
Array ( [id] => 1004682 [patent_doc_number] => 06910121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions' [patent_app_type] => utility [patent_app_number] => 10/039113 [patent_app_country] => US [patent_app_date] => 2002-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3603 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/910/06910121.pdf [firstpage_image] =>[orig_patent_app_number] => 10039113 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/039113
System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions Jan 1, 2002 Issued
Array ( [id] => 6283223 [patent_doc_number] => 20020108029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Program counter (PC) relative addressing mode with fast displacement' [patent_app_type] => new [patent_app_number] => 10/017198 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5269 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20020108029.pdf [firstpage_image] =>[orig_patent_app_number] => 10017198 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017198
Program counter (PC) relative addressing mode with fast displacement Dec 17, 2001 Issued
Array ( [id] => 7412128 [patent_doc_number] => 20040024935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Programmable controller' [patent_app_type] => new [patent_app_number] => 10/203407 [patent_app_country] => US [patent_app_date] => 2002-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16143 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20040024935.pdf [firstpage_image] =>[orig_patent_app_number] => 10203407 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/203407
Programmable controller Nov 20, 2001 Issued
Array ( [id] => 6862644 [patent_doc_number] => 20030093652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Operand file using pointers and reference counters and a method of use' [patent_app_type] => new [patent_app_number] => 10/004338 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5119 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20030093652.pdf [firstpage_image] =>[orig_patent_app_number] => 10004338 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/004338
Operand file using pointers and reference counters and a method of use Nov 13, 2001 Issued
Array ( [id] => 937578 [patent_doc_number] => 06976154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Pipelined processor for examining packet header information' [patent_app_type] => utility [patent_app_number] => 09/986019 [patent_app_country] => US [patent_app_date] => 2001-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5447 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/976/06976154.pdf [firstpage_image] =>[orig_patent_app_number] => 09986019 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986019
Pipelined processor for examining packet header information Nov 6, 2001 Issued
Array ( [id] => 8678617 [patent_doc_number] => 08386752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Processor architecture' [patent_app_type] => utility [patent_app_number] => 10/450615 [patent_app_country] => US [patent_app_date] => 2001-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6880 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10450615 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/450615
Processor architecture Oct 18, 2001 Issued
Array ( [id] => 792693 [patent_doc_number] => 06986022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-10 [patent_title] => 'Boundary synchronization mechanism for a processor of a systolic array' [patent_app_type] => utility [patent_app_number] => 09/978640 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/986/06986022.pdf [firstpage_image] =>[orig_patent_app_number] => 09978640 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978640
Boundary synchronization mechanism for a processor of a systolic array Oct 15, 2001 Issued
Array ( [id] => 6424602 [patent_doc_number] => 20020126705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Synchronous network traffic processor' [patent_app_type] => new [patent_app_number] => 09/976765 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11562 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20020126705.pdf [firstpage_image] =>[orig_patent_app_number] => 09976765 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976765
Synchronous network traffic processor Oct 11, 2001 Issued
Array ( [id] => 6814995 [patent_doc_number] => 20030074545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Method and apparatus for binding shadow registers to vectored interrupts' [patent_app_type] => new [patent_app_number] => 09/977084 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5928 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074545.pdf [firstpage_image] =>[orig_patent_app_number] => 09977084 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977084
Method and apparatus for binding shadow registers to vectored interrupts Oct 11, 2001 Issued
Array ( [id] => 955144 [patent_doc_number] => 06959376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-25 [patent_title] => 'Integrated circuit containing multiple digital signal processors' [patent_app_type] => utility [patent_app_number] => 09/975677 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/959/06959376.pdf [firstpage_image] =>[orig_patent_app_number] => 09975677 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975677
Integrated circuit containing multiple digital signal processors Oct 10, 2001 Issued
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