Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5861270 [patent_doc_number] => 20020124155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Processor architecture' [patent_app_type] => new [patent_app_number] => 09/976241 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6212 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124155.pdf [firstpage_image] =>[orig_patent_app_number] => 09976241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976241
Processor architecture Oct 10, 2001 Issued
Array ( [id] => 5816216 [patent_doc_number] => 20020040428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-04 [patent_title] => 'Computer system and method of controlling computation' [patent_app_type] => new [patent_app_number] => 09/964749 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8610 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20020040428.pdf [firstpage_image] =>[orig_patent_app_number] => 09964749 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964749
Computer system and method of controlling computation Sep 27, 2001 Issued
Array ( [id] => 6784461 [patent_doc_number] => 20030065909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Deferral of dependent loads until after execution of colliding stores' [patent_app_type] => new [patent_app_number] => 09/964807 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2219 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065909.pdf [firstpage_image] =>[orig_patent_app_number] => 09964807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964807
Deferral of dependent loads until after execution of colliding stores Sep 27, 2001 Abandoned
Array ( [id] => 7626823 [patent_doc_number] => 06807621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Pipelined microprocessor and a method relating thereto' [patent_app_type] => B2 [patent_app_number] => 09/965961 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8354 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807621.pdf [firstpage_image] =>[orig_patent_app_number] => 09965961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965961
Pipelined microprocessor and a method relating thereto Sep 26, 2001 Issued
Array ( [id] => 6606740 [patent_doc_number] => 20020042872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Renaming apparatus and processor' [patent_app_type] => new [patent_app_number] => 09/962197 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4630 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20020042872.pdf [firstpage_image] =>[orig_patent_app_number] => 09962197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/962197
Renaming apparatus and processor Sep 25, 2001 Issued
Array ( [id] => 6675863 [patent_doc_number] => 20030061466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Method and apparatus for fast dependency cooridnate matching' [patent_app_type] => new [patent_app_number] => 09/965211 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4884 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061466.pdf [firstpage_image] =>[orig_patent_app_number] => 09965211 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965211
Method and apparatus for fast dependency coordinate matching Sep 25, 2001 Issued
Array ( [id] => 6899303 [patent_doc_number] => 20010047468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Branch and return on blocked load or store' [patent_app_type] => new [patent_app_number] => 09/925090 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2803 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047468.pdf [firstpage_image] =>[orig_patent_app_number] => 09925090 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/925090
Branch and return on blocked load or store Aug 7, 2001 Issued
Array ( [id] => 1024933 [patent_doc_number] => 06889318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Instruction fusion for digital signal processor' [patent_app_type] => utility [patent_app_number] => 09/924178 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2313 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/889/06889318.pdf [firstpage_image] =>[orig_patent_app_number] => 09924178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924178
Instruction fusion for digital signal processor Aug 6, 2001 Issued
Array ( [id] => 548912 [patent_doc_number] => 07185183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-27 [patent_title] => 'Atomic update of CPO state' [patent_app_type] => utility [patent_app_number] => 09/921400 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7869 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185183.pdf [firstpage_image] =>[orig_patent_app_number] => 09921400 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921400
Atomic update of CPO state Aug 1, 2001 Issued
Array ( [id] => 554189 [patent_doc_number] => 07181600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-20 [patent_title] => 'Read-only access to CPO registers' [patent_app_type] => utility [patent_app_number] => 09/921377 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5375 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/181/07181600.pdf [firstpage_image] =>[orig_patent_app_number] => 09921377 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921377
Read-only access to CPO registers Aug 1, 2001 Issued
Array ( [id] => 6751997 [patent_doc_number] => 20030046518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Look-ahead load pre-fetch in a processor' [patent_app_type] => new [patent_app_number] => 09/922551 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1979 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20030046518.pdf [firstpage_image] =>[orig_patent_app_number] => 09922551 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922551
Look-ahead load pre-fetch in a processor Aug 1, 2001 Issued
Array ( [id] => 995900 [patent_doc_number] => 06918027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'System and method for in-system programming through an on-system JTAG bridge of programmable logic devices on multiple circuit boards of a system' [patent_app_type] => utility [patent_app_number] => 09/917983 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5732 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/918/06918027.pdf [firstpage_image] =>[orig_patent_app_number] => 09917983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917983
System and method for in-system programming through an on-system JTAG bridge of programmable logic devices on multiple circuit boards of a system Jul 29, 2001 Issued
Array ( [id] => 462324 [patent_doc_number] => 07246220 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-17 [patent_title] => 'Architecture for hardware-assisted context switching between register groups dedicated to time-critical or non-time critical tasks without saving state' [patent_app_type] => utility [patent_app_number] => 09/917312 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3942 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/246/07246220.pdf [firstpage_image] =>[orig_patent_app_number] => 09917312 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917312
Architecture for hardware-assisted context switching between register groups dedicated to time-critical or non-time critical tasks without saving state Jul 26, 2001 Issued
Array ( [id] => 6006081 [patent_doc_number] => 20110119471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'Method and apparatus to extract integer and fractional components from floating-point data' [patent_app_type] => utility [patent_app_number] => 10/483279 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3831 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119471.pdf [firstpage_image] =>[orig_patent_app_number] => 10483279 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/483279
Method and apparatus to extract integer and fractional components from floating-point data Jul 12, 2001 Issued
Array ( [id] => 1444116 [patent_doc_number] => 06496918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Intermediate-grain reconfigurable processing device' [patent_app_type] => B1 [patent_app_number] => 09/892812 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 38 [patent_no_of_words] => 15297 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496918.pdf [firstpage_image] =>[orig_patent_app_number] => 09892812 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892812
Intermediate-grain reconfigurable processing device Jun 26, 2001 Issued
Array ( [id] => 6899206 [patent_doc_number] => 20010047371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Electronic document circulating system' [patent_app_type] => new [patent_app_number] => 09/880773 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11876 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047371.pdf [firstpage_image] =>[orig_patent_app_number] => 09880773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880773
Electronic document circulating system Jun 14, 2001 Issued
Array ( [id] => 721738 [patent_doc_number] => 07055020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Flushable free register list having selected pointers moving in unison' [patent_app_type] => utility [patent_app_number] => 09/881071 [patent_app_country] => US [patent_app_date] => 2001-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5007 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/055/07055020.pdf [firstpage_image] =>[orig_patent_app_number] => 09881071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/881071
Flushable free register list having selected pointers moving in unison Jun 12, 2001 Issued
Array ( [id] => 1055833 [patent_doc_number] => 06859873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Variable length instruction pipeline' [patent_app_type] => utility [patent_app_number] => 09/878145 [patent_app_country] => US [patent_app_date] => 2001-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 4496 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859873.pdf [firstpage_image] =>[orig_patent_app_number] => 09878145 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878145
Variable length instruction pipeline Jun 7, 2001 Issued
Array ( [id] => 6746653 [patent_doc_number] => 20030023836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Shadow register array control instructions' [patent_app_type] => new [patent_app_number] => 09/870463 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20030023836.pdf [firstpage_image] =>[orig_patent_app_number] => 09870463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870463
Shadow register array control instructions May 31, 2001 Abandoned
Array ( [id] => 6689780 [patent_doc_number] => 20030033506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Locking source registers in a data processing apparatus' [patent_app_type] => new [patent_app_number] => 09/860777 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11343 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20030033506.pdf [firstpage_image] =>[orig_patent_app_number] => 09860777 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/860777
Locking source registers in a data processing apparatus May 20, 2001 Issued
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