Eliseo Ramos Feliciano

Array ( [id] => 7341013 [patent_doc_number] => 20040133673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Apparatus and method for processing pipelined data' [patent_app_type] => new [patent_app_number] => 10/470096 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4683 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20040133673.pdf [firstpage_image] =>[orig_patent_app_number] => 10470096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7368835 [patent_doc_number] => 20040015904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Method and apparatus for optimizing load memory accesses' [patent_app_type] => new [patent_app_number] => 09/861050 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4294 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015904.pdf [firstpage_image] =>[orig_patent_app_number] => 09861050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1170181 [patent_doc_number] => 06766443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Compression of execution path history to improve branch prediction accuracy' [patent_app_type] => B2 [patent_app_number] => 09/859247 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5675 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766443.pdf [firstpage_image] =>[orig_patent_app_number] => 09859247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 508228 [patent_doc_number] => 07210022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Apparatus and method for interconnecting a processor to co-processors using a shared memory as the communication interface' [patent_app_type] => utility [patent_app_number] => 09/858308 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 15101 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/210/07210022.pdf [firstpage_image] =>[orig_patent_app_number] => 09858308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7615396 [patent_doc_number] => 06948051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-20 [patent_title] => 'Method and apparatus for reducing logic activity in a microprocessor using reduced bit width slices that are enabled or disabled depending on operation width' [patent_app_type] => utility [patent_app_number] => 09/855241 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/948/06948051.pdf [firstpage_image] =>[orig_patent_app_number] => 09855241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6935302 [patent_doc_number] => 20010056458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Method and system for controlling parallel execution of jobs' [patent_app_type] => new [patent_app_number] => 09/852662 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5640 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20010056458.pdf [firstpage_image] =>[orig_patent_app_number] => 09852662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7621141 [patent_doc_number] => 06978360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Scalable processor' [patent_app_type] => utility [patent_app_number] => 09/854243 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3411 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/978/06978360.pdf [firstpage_image] =>[orig_patent_app_number] => 09854243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5803520 [patent_doc_number] => 20020010847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Executing partial-width packed data instructions' [patent_app_type] => new [patent_app_number] => 09/852217 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8893 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010847.pdf [firstpage_image] =>[orig_patent_app_number] => 09852217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1079239 [patent_doc_number] => RE038679 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2004-12-28 [patent_title] => 'Data processor and method of processing data' [patent_app_type] => E1 [patent_app_number] => 09/848253 [patent_app_country] => US [patent_app_date] => 2001-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 58 [patent_no_of_words] => 18112 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038679.pdf [firstpage_image] =>[orig_patent_app_number] => 09848253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7001740 [patent_doc_number] => 20010054124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Parallel processor system' [patent_app_type] => new [patent_app_number] => 09/847397 [patent_app_country] => US [patent_app_date] => 2001-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5819 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054124.pdf [firstpage_image] =>[orig_patent_app_number] => 09847397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1521610 [patent_doc_number] => 06502136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'EXCLUSIVE CONTROL METHOD WITH EACH NODE CONTROLLING ISSUE OF AN EXCLUSIVE USE REQUEST TO A SHARED RESOURCE, A COMPUTER SYSTEM THEREFOR AND A COMPUTER SYSTEM WITH A CIRCUIT FOR DETECTING WRITING OF AN EVENT FLAG INTO A SHARED MAIN STORAGE' [patent_app_type] => B1 [patent_app_number] => 09/846261 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 23373 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502136.pdf [firstpage_image] =>[orig_patent_app_number] => 09846261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 667203 [patent_doc_number] => 07103883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'System and method for translating include files' [patent_app_type] => utility [patent_app_number] => 09/846743 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 13635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/103/07103883.pdf [firstpage_image] =>[orig_patent_app_number] => 09846743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7645882 [patent_doc_number] => 06477641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Method for translating between source and target code with heterogenous register sets' [patent_app_type] => B2 [patent_app_number] => 09/846752 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 13587 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477641.pdf [firstpage_image] =>[orig_patent_app_number] => 09846752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 126740 [patent_doc_number] => 07711926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Mapping system and method for instruction set processing' [patent_app_type] => utility [patent_app_number] => 09/836541 [patent_app_country] => US [patent_app_date] => 2001-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4537 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/711/07711926.pdf [firstpage_image] =>[orig_patent_app_number] => 09836541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6881021 [patent_doc_number] => 20010032309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Static branch prediction mechanism for conditional branch instructions' [patent_app_type] => new [patent_app_number] => 09/825435 [patent_app_country] => US [patent_app_date] => 2001-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10769 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032309.pdf [firstpage_image] =>[orig_patent_app_number] => 09825435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 995899 [patent_doc_number] => 06918026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'External device transmission system and a fast pattern processor employing the same' [patent_app_type] => utility [patent_app_number] => 09/821893 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4565 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/918/06918026.pdf [firstpage_image] =>[orig_patent_app_number] => 09821893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1225658 [patent_doc_number] => 06704853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Digital signal processing apparatus and method for controlling the same' [patent_app_type] => B1 [patent_app_number] => 09/806310 [patent_app_country] => US [patent_app_date] => 2001-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4141 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704853.pdf [firstpage_image] =>[orig_patent_app_number] => 09806310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5890343 [patent_doc_number] => 20020013891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Configurable hardware block' [patent_app_type] => new [patent_app_number] => 09/816926 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9658 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013891.pdf [firstpage_image] =>[orig_patent_app_number] => 09816926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1109838 [patent_doc_number] => 06813707 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Enhancing instruction execution using built-in macros' [patent_app_type] => B1 [patent_app_number] => 09/681348 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4472 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813707.pdf [firstpage_image] =>[orig_patent_app_number] => 09681348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6561452 [patent_doc_number] => 20020138718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Storage system for use in custom loop accelerators and the like' [patent_app_type] => new [patent_app_number] => 09/816851 [patent_app_country] => US [patent_app_date] => 2001-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3198 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138718.pdf [firstpage_image] =>[orig_patent_app_number] => 09816851 [rel_patent_id] =>[rel_patent_doc_number] =>)