Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6900406 [patent_doc_number] => 20010010082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Microprocessor including controller for reduced power consumption and method therefor' [patent_app_type] => new [patent_app_number] => 09/805200 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6974 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20010010082.pdf [firstpage_image] =>[orig_patent_app_number] => 09805200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805200
Microprocessor including microcode unit that only changes the value of control signals required for the current cycle operation for reduced power consumption and method therefor Mar 13, 2001 Issued
Array ( [id] => 1587488 [patent_doc_number] => 06425073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method and apparatus for staggering execution of an instruction' [patent_app_type] => B1 [patent_app_number] => 09/805280 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6939 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425073.pdf [firstpage_image] =>[orig_patent_app_number] => 09805280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805280
Method and apparatus for staggering execution of an instruction Mar 12, 2001 Issued
Array ( [id] => 1106252 [patent_doc_number] => 06816961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Processing architecture having field swapping capability' [patent_app_type] => B2 [patent_app_number] => 09/802121 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5043 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816961.pdf [firstpage_image] =>[orig_patent_app_number] => 09802121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802121
Processing architecture having field swapping capability Mar 7, 2001 Issued
Array ( [id] => 6065259 [patent_doc_number] => 20020032558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Method and apparatus for enhancing the performance of a pipelined data processor' [patent_app_type] => new [patent_app_number] => 09/802046 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13352 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20020032558.pdf [firstpage_image] =>[orig_patent_app_number] => 09802046 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802046
Method and apparatus for enhancing the performance of a pipelined data processor Mar 7, 2001 Abandoned
Array ( [id] => 5861285 [patent_doc_number] => 20020124161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Data processing system having redirecting circuitry and method therefor' [patent_app_type] => new [patent_app_number] => 09/798390 [patent_app_country] => US [patent_app_date] => 2001-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6552 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124161.pdf [firstpage_image] =>[orig_patent_app_number] => 09798390 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798390
Data processing system having redirecting circuitry and method therefor Mar 4, 2001 Issued
Array ( [id] => 5803522 [patent_doc_number] => 20020010849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Data object architecture and method for xDSL ASIC processor' [patent_app_type] => new [patent_app_number] => 09/797755 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 24337 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010849.pdf [firstpage_image] =>[orig_patent_app_number] => 09797755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797755
Data object architecture and method for xDSL ASIC processor Feb 28, 2001 Issued
Array ( [id] => 1075162 [patent_doc_number] => 06839830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Logical pipeline for data communications system' [patent_app_type] => utility [patent_app_number] => 09/798054 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 24281 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839830.pdf [firstpage_image] =>[orig_patent_app_number] => 09798054 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798054
Logical pipeline for data communications system Feb 28, 2001 Issued
Array ( [id] => 7610014 [patent_doc_number] => 06842845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Methods and apparatuses for signal processing' [patent_app_type] => utility [patent_app_number] => 09/792839 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 9770 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842845.pdf [firstpage_image] =>[orig_patent_app_number] => 09792839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/792839
Methods and apparatuses for signal processing Feb 22, 2001 Issued
Array ( [id] => 597408 [patent_doc_number] => 07444156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'User-tagging of cellular telephone locations' [patent_app_type] => utility [patent_app_number] => 09/789434 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4778 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/444/07444156.pdf [firstpage_image] =>[orig_patent_app_number] => 09789434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789434
User-tagging of cellular telephone locations Feb 19, 2001 Issued
Array ( [id] => 1466294 [patent_doc_number] => 06393546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values' [patent_app_type] => B1 [patent_app_number] => 09/788067 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13034 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393546.pdf [firstpage_image] =>[orig_patent_app_number] => 09788067 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788067
Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values Feb 15, 2001 Issued
Array ( [id] => 7029753 [patent_doc_number] => 20010014938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'Microprocessor' [patent_app_type] => new [patent_app_number] => 09/775836 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4062 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014938.pdf [firstpage_image] =>[orig_patent_app_number] => 09775836 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775836
Microprocessor Feb 1, 2001 Issued
Array ( [id] => 6881018 [patent_doc_number] => 20010032306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Memory disambiguation scheme for partially redundant load removal' [patent_app_type] => new [patent_app_number] => 09/755774 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4272 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032306.pdf [firstpage_image] =>[orig_patent_app_number] => 09755774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755774
Memory disambiguation scheme for partially redundant load removal Jan 4, 2001 Issued
Array ( [id] => 5861271 [patent_doc_number] => 20020124156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Using \"silent store\" information to advance loads' [patent_app_type] => new [patent_app_number] => 09/752796 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3566 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124156.pdf [firstpage_image] =>[orig_patent_app_number] => 09752796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752796
Prediction of issued silent store operations for allowing subsequently issued loads to bypass unexecuted silent stores and confirming the bypass upon execution of the stores Dec 28, 2000 Issued
Array ( [id] => 989521 [patent_doc_number] => 06922773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'System and method for encoding constant operands in a wide issue processor' [patent_app_type] => utility [patent_app_number] => 09/751408 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9348 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/922/06922773.pdf [firstpage_image] =>[orig_patent_app_number] => 09751408 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751408
System and method for encoding constant operands in a wide issue processor Dec 28, 2000 Issued
Array ( [id] => 6648617 [patent_doc_number] => 20020087827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Architecture of psm-mpus and coprocessors' [patent_app_type] => new [patent_app_number] => 09/751943 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087827.pdf [firstpage_image] =>[orig_patent_app_number] => 09751943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751943
Multiple coprocessor architecture to process a plurality of subtasks in parallel Dec 27, 2000 Issued
Array ( [id] => 6839885 [patent_doc_number] => 20030037225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Apparatus and method for microcontroller debugging' [patent_app_type] => new [patent_app_number] => 09/752567 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037225.pdf [firstpage_image] =>[orig_patent_app_number] => 09752567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752567
Apparatus and method for microcontroller debugging Dec 27, 2000 Issued
Array ( [id] => 6226775 [patent_doc_number] => 20020004897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Data processing apparatus for executing multiple instruction sets' [patent_app_type] => new [patent_app_number] => 09/749674 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4178 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004897.pdf [firstpage_image] =>[orig_patent_app_number] => 09749674 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749674
Data processing apparatus for executing multiple instruction sets Dec 26, 2000 Abandoned
Array ( [id] => 7105728 [patent_doc_number] => 20010004756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'Instruction processing apparatus' [patent_app_type] => new-utility [patent_app_number] => 09/739800 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7323 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004756.pdf [firstpage_image] =>[orig_patent_app_number] => 09739800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739800
Instruction processing apparatus Dec 19, 2000 Issued
Array ( [id] => 1430455 [patent_doc_number] => 06526502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Apparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcome' [patent_app_type] => B1 [patent_app_number] => 09/690371 [patent_app_country] => US [patent_app_date] => 2000-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7843 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526502.pdf [firstpage_image] =>[orig_patent_app_number] => 09690371 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690371
Apparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcome Dec 15, 2000 Issued
Array ( [id] => 1460051 [patent_doc_number] => 06463519 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Multi-CPU unit' [patent_app_type] => B1 [patent_app_number] => 09/736452 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8762 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463519.pdf [firstpage_image] =>[orig_patent_app_number] => 09736452 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736452
Multi-CPU unit Dec 14, 2000 Issued
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