Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7105729 [patent_doc_number] => 20010004757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'Processor and method of controlling the same' [patent_app_type] => new-utility [patent_app_number] => 09/736357 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 30013 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004757.pdf [firstpage_image] =>[orig_patent_app_number] => 09736357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736357
Processor and method of controlling the same Dec 14, 2000 Issued
Array ( [id] => 6051469 [patent_doc_number] => 20020169946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Methods, systems, and computer program products for compressing a computer program based on a compression criterion and executing the compressed program' [patent_app_type] => new [patent_app_number] => 09/736682 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11953 [patent_no_of_claims] => 81 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20020169946.pdf [firstpage_image] =>[orig_patent_app_number] => 09736682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736682
Methods, systems, and computer program products for compressing a computer program based on a compression criterion and executing the compressed program Dec 12, 2000 Issued
Array ( [id] => 940475 [patent_doc_number] => 06973561 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Processor pipeline stall based on data register status' [patent_app_type] => utility [patent_app_number] => 09/729508 [patent_app_country] => US [patent_app_date] => 2000-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3075 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/973/06973561.pdf [firstpage_image] =>[orig_patent_app_number] => 09729508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/729508
Processor pipeline stall based on data register status Dec 3, 2000 Issued
Array ( [id] => 1181183 [patent_doc_number] => 06754809 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Data processing apparatus with indirect register file access' [patent_app_type] => B1 [patent_app_number] => 09/713442 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 8889 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754809.pdf [firstpage_image] =>[orig_patent_app_number] => 09713442 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713442
Data processing apparatus with indirect register file access Nov 14, 2000 Issued
Array ( [id] => 744985 [patent_doc_number] => 07035998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'Clustering stream and/or instruction queues for multi-streaming processors' [patent_app_type] => utility [patent_app_number] => 09/706157 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035998.pdf [firstpage_image] =>[orig_patent_app_number] => 09706157 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706157
Clustering stream and/or instruction queues for multi-streaming processors Nov 2, 2000 Issued
Array ( [id] => 626399 [patent_doc_number] => 07139898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-21 [patent_title] => 'Fetch and dispatch disassociation apparatus for multistreaming processors' [patent_app_type] => utility [patent_app_number] => 09/706154 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2081 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139898.pdf [firstpage_image] =>[orig_patent_app_number] => 09706154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/706154
Fetch and dispatch disassociation apparatus for multistreaming processors Nov 2, 2000 Issued
Array ( [id] => 1170187 [patent_doc_number] => 06766444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Hardware loops' [patent_app_type] => B1 [patent_app_number] => 09/705070 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 8216 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766444.pdf [firstpage_image] =>[orig_patent_app_number] => 09705070 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705070
Hardware loops Nov 1, 2000 Issued
Array ( [id] => 7613838 [patent_doc_number] => 06898693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-24 [patent_title] => 'Hardware loops' [patent_app_type] => utility [patent_app_number] => 09/705088 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 8218 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898693.pdf [firstpage_image] =>[orig_patent_app_number] => 09705088 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705088
Hardware loops Nov 1, 2000 Issued
Array ( [id] => 1184825 [patent_doc_number] => 06748523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Hardware loops' [patent_app_type] => B1 [patent_app_number] => 09/705217 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 8223 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748523.pdf [firstpage_image] =>[orig_patent_app_number] => 09705217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705217
Hardware loops Nov 1, 2000 Issued
Array ( [id] => 1506007 [patent_doc_number] => 06487651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'MIMD arrangement of SIMD machines' [patent_app_type] => B1 [patent_app_number] => 09/696078 [patent_app_country] => US [patent_app_date] => 2000-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4769 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487651.pdf [firstpage_image] =>[orig_patent_app_number] => 09696078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/696078
MIMD arrangement of SIMD machines Oct 24, 2000 Issued
Array ( [id] => 1377378 [patent_doc_number] => 06578139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/691375 [patent_app_country] => US [patent_app_date] => 2000-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2916 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578139.pdf [firstpage_image] =>[orig_patent_app_number] => 09691375 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/691375
Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor Oct 17, 2000 Issued
Array ( [id] => 1552984 [patent_doc_number] => 06446191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication' [patent_app_type] => B1 [patent_app_number] => 09/677732 [patent_app_country] => US [patent_app_date] => 2000-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8571 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446191.pdf [firstpage_image] =>[orig_patent_app_number] => 09677732 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/677732
Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication Oct 1, 2000 Issued
09/672424 COMPLEX INSTRUCTION SET COMPUTER Sep 27, 2000 Abandoned
Array ( [id] => 481354 [patent_doc_number] => 07228404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-05 [patent_title] => 'Managing instruction side-effects' [patent_app_type] => utility [patent_app_number] => 09/672440 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 61 [patent_no_of_words] => 88520 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228404.pdf [firstpage_image] =>[orig_patent_app_number] => 09672440 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672440
Managing instruction side-effects Sep 27, 2000 Issued
Array ( [id] => 978766 [patent_doc_number] => 06934832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-23 [patent_title] => 'Exception mechanism for a computer' [patent_app_type] => utility [patent_app_number] => 09/667226 [patent_app_country] => US [patent_app_date] => 2000-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 61 [patent_no_of_words] => 88654 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934832.pdf [firstpage_image] =>[orig_patent_app_number] => 09667226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/667226
Exception mechanism for a computer Sep 20, 2000 Issued
Array ( [id] => 7623811 [patent_doc_number] => 06725366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'System and method for 32 bit code branching to 64 bit targets' [patent_app_type] => B1 [patent_app_number] => 09/657115 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4573 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725366.pdf [firstpage_image] =>[orig_patent_app_number] => 09657115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657115
System and method for 32 bit code branching to 64 bit targets Sep 6, 2000 Issued
Array ( [id] => 1279668 [patent_doc_number] => 06654878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Register bit scanning' [patent_app_type] => B1 [patent_app_number] => 09/657117 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3031 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654878.pdf [firstpage_image] =>[orig_patent_app_number] => 09657117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657117
Register bit scanning Sep 6, 2000 Issued
Array ( [id] => 568504 [patent_doc_number] => 07171541 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-30 [patent_title] => 'Register renaming system' [patent_app_type] => utility [patent_app_number] => 10/069987 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2747 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/171/07171541.pdf [firstpage_image] =>[orig_patent_app_number] => 10069987 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/069987
Register renaming system Sep 5, 2000 Issued
Array ( [id] => 1186687 [patent_doc_number] => 06738894 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Data processor' [patent_app_type] => B1 [patent_app_number] => 09/655465 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 16453 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738894.pdf [firstpage_image] =>[orig_patent_app_number] => 09655465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655465
Data processor Sep 4, 2000 Issued
Array ( [id] => 548856 [patent_doc_number] => 07185179 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-27 [patent_title] => 'Architecture of a parallel computer and an information processing unit using the same' [patent_app_type] => utility [patent_app_number] => 10/088028 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 41 [patent_no_of_words] => 11367 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185179.pdf [firstpage_image] =>[orig_patent_app_number] => 10088028 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/088028
Architecture of a parallel computer and an information processing unit using the same Aug 31, 2000 Issued
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