Eliseo Ramos Feliciano

Array ( [id] => 1284645 [patent_doc_number] => 06651160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Register set extension for compressed instruction set' [patent_app_type] => B1 [patent_app_number] => 09/654064 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3277 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651160.pdf [firstpage_image] =>[orig_patent_app_number] => 09654064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1186688 [patent_doc_number] => 06738895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Method and system for substantially registerless processing' [patent_app_type] => B1 [patent_app_number] => 09/655004 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6879 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738895.pdf [firstpage_image] =>[orig_patent_app_number] => 09655004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1183602 [patent_doc_number] => 06751721 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Broadcast invalidate scheme' [patent_app_type] => B1 [patent_app_number] => 09/652165 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9600 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751721.pdf [firstpage_image] =>[orig_patent_app_number] => 09652165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 294144 [patent_doc_number] => 07546444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-09 [patent_title] => 'Register set used in multithreaded parallel processor architecture' [patent_app_type] => utility [patent_app_number] => 10/070091 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546444.pdf [firstpage_image] =>[orig_patent_app_number] => 10070091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4298981 [patent_doc_number] => 06282638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Virtual shadow registers and virtual register windows' [patent_app_type] => 1 [patent_app_number] => 9/653089 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14335 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282638.pdf [firstpage_image] =>[orig_patent_app_number] => 653089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7611328 [patent_doc_number] => 06904514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-07 [patent_title] => 'Data processor' [patent_app_type] => utility [patent_app_number] => 09/830704 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 14220 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904514.pdf [firstpage_image] =>[orig_patent_app_number] => 09830704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1181138 [patent_doc_number] => 06754801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method and apparatus for a shift register based interconnection for a massively parallel processor array' [patent_app_type] => B1 [patent_app_number] => 09/642774 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3131 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754801.pdf [firstpage_image] =>[orig_patent_app_number] => 09642774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422667 [patent_doc_number] => 06272621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Synchronization and control system for an arrayed processing engine' [patent_app_type] => 1 [patent_app_number] => 9/642144 [patent_app_country] => US [patent_app_date] => 2000-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8014 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272621.pdf [firstpage_image] =>[orig_patent_app_number] => 642144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1444066 [patent_doc_number] => 06336212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Self modifying code to test all possible addressing modes' [patent_app_type] => B1 [patent_app_number] => 09/639390 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4238 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/336/06336212.pdf [firstpage_image] =>[orig_patent_app_number] => 09639390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7623814 [patent_doc_number] => 06725363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Method for filtering instructions to get more precise event counts' [patent_app_type] => B1 [patent_app_number] => 09/629317 [patent_app_country] => US [patent_app_date] => 2000-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2599 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725363.pdf [firstpage_image] =>[orig_patent_app_number] => 09629317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4292342 [patent_doc_number] => 06247106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Processor configured to map logical register numbers to physical register numbers using virtual register numbers' [patent_app_type] => 1 [patent_app_number] => 9/626556 [patent_app_country] => US [patent_app_date] => 2000-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 16535 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247106.pdf [firstpage_image] =>[orig_patent_app_number] => 626556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7622355 [patent_doc_number] => 06687811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Processor with trace memory for storing access information on internal bus' [patent_app_type] => B1 [patent_app_number] => 09/624602 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 10643 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687811.pdf [firstpage_image] =>[orig_patent_app_number] => 09624602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1116650 [patent_doc_number] => 06804771 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Processor with register file accessible by row column to achieve data array transposition' [patent_app_type] => B1 [patent_app_number] => 09/626263 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4739 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/804/06804771.pdf [firstpage_image] =>[orig_patent_app_number] => 09626263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1291981 [patent_doc_number] => 06643764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Multiprocessor system utilizing multiple links to improve point to point bandwidth' [patent_app_type] => B1 [patent_app_number] => 09/620372 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3108 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643764.pdf [firstpage_image] =>[orig_patent_app_number] => 09620372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 744981 [patent_doc_number] => 07035997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors' [patent_app_type] => utility [patent_app_number] => 09/616385 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5910 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035997.pdf [firstpage_image] =>[orig_patent_app_number] => 09616385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1210398 [patent_doc_number] => 06718455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Multimedia-instruction acceleration device and method thereof' [patent_app_type] => B1 [patent_app_number] => 09/614540 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2300 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718455.pdf [firstpage_image] =>[orig_patent_app_number] => 09614540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424614 [patent_doc_number] => 06266765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Computer architecture capable of execution of general purpose multiple instructions' [patent_app_type] => 1 [patent_app_number] => 9/611378 [patent_app_country] => US [patent_app_date] => 2000-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 7392 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266765.pdf [firstpage_image] =>[orig_patent_app_number] => 611378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1308959 [patent_doc_number] => 06629232 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Copied register files for data processors having many execution units' [patent_app_type] => B1 [patent_app_number] => 09/609911 [patent_app_country] => US [patent_app_date] => 2000-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2941 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629232.pdf [firstpage_image] =>[orig_patent_app_number] => 09609911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1250265 [patent_doc_number] => 06675289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'System and method for executing hybridized code on a dynamically configurable hardware environment' [patent_app_type] => B1 [patent_app_number] => 09/608860 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 8611 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675289.pdf [firstpage_image] =>[orig_patent_app_number] => 09608860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1279606 [patent_doc_number] => 06654870 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Methods and apparatus for establishing port priority functions in a VLIW processor' [patent_app_type] => B1 [patent_app_number] => 09/598084 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6605 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654870.pdf [firstpage_image] =>[orig_patent_app_number] => 09598084 [rel_patent_id] =>[rel_patent_doc_number] =>)