Eliseo Ramos Feliciano

Array ( [id] => 4381456 [patent_doc_number] => 06256721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Register renaming in which moves are accomplished by swapping tags' [patent_app_type] => 1 [patent_app_number] => 9/595726 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15973 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256721.pdf [firstpage_image] =>[orig_patent_app_number] => 595726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4298756 [patent_doc_number] => 06282627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Integrated processor and programmable data path chip for reconfigurable computing' [patent_app_type] => 1 [patent_app_number] => 9/446762 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 5683 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282627.pdf [firstpage_image] =>[orig_patent_app_number] => 446762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4388416 [patent_doc_number] => 06275920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Mesh connected computed' [patent_app_type] => 1 [patent_app_number] => 9/552319 [patent_app_country] => US [patent_app_date] => 2000-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 75 [patent_no_of_words] => 68062 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275920.pdf [firstpage_image] =>[orig_patent_app_number] => 552319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587292 [patent_doc_number] => 06425026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Distribution, processing, and reconstruction of variable-sized images using multiple processor arrays' [patent_app_type] => B1 [patent_app_number] => 09/511697 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14312 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425026.pdf [firstpage_image] =>[orig_patent_app_number] => 09511697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1234303 [patent_doc_number] => 06697929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Scannable zero-catcher and one-catcher circuits for reduced clock loading and power dissipation' [patent_app_type] => B1 [patent_app_number] => 09/504004 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5418 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/697/06697929.pdf [firstpage_image] =>[orig_patent_app_number] => 09504004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1169808 [patent_doc_number] => 06763448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Microcomputer and microcomputer system' [patent_app_type] => B1 [patent_app_number] => 09/503358 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 27701 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763448.pdf [firstpage_image] =>[orig_patent_app_number] => 09503358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7626824 [patent_doc_number] => 06807620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Game system with graphics processor' [patent_app_type] => B1 [patent_app_number] => 09/502671 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 10674 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807620.pdf [firstpage_image] =>[orig_patent_app_number] => 09502671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1161672 [patent_doc_number] => 06775765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Data processing system having instruction folding and method thereof' [patent_app_type] => B1 [patent_app_number] => 09/498814 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 11189 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775765.pdf [firstpage_image] =>[orig_patent_app_number] => 09498814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1337287 [patent_doc_number] => 06604191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Method and apparatus for accelerating instruction fetching for a processor' [patent_app_type] => B1 [patent_app_number] => 09/498932 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4698 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604191.pdf [firstpage_image] =>[orig_patent_app_number] => 09498932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1314616 [patent_doc_number] => 06622240 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method and apparatus for pre-branch instruction' [patent_app_type] => B1 [patent_app_number] => 09/496008 [patent_app_country] => US [patent_app_date] => 2000-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4810 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622240.pdf [firstpage_image] =>[orig_patent_app_number] => 09496008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1348193 [patent_doc_number] => 06598155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method and apparatus for loop buffering digital signal processing instructions' [patent_app_type] => B1 [patent_app_number] => 09/494609 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 10414 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598155.pdf [firstpage_image] =>[orig_patent_app_number] => 09494609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1540608 [patent_doc_number] => 06490674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'System and method for coalescing data utilized to detect data hazards' [patent_app_type] => B1 [patent_app_number] => 09/493504 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 15748 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490674.pdf [firstpage_image] =>[orig_patent_app_number] => 09493504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1319130 [patent_doc_number] => 06618800 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Procedure and processor arrangement for parallel data processing' [patent_app_type] => B1 [patent_app_number] => 09/484776 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4133 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618800.pdf [firstpage_image] =>[orig_patent_app_number] => 09484776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1308956 [patent_doc_number] => 06629231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'System and method for efficient register file conversion of denormal numbers between scalar and SIMD formats' [patent_app_type] => B1 [patent_app_number] => 09/477496 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6136 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629231.pdf [firstpage_image] =>[orig_patent_app_number] => 09477496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1243161 [patent_doc_number] => 06684321 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Unified memory architecture for use by a main processor and an external processor and method of operation' [patent_app_type] => B1 [patent_app_number] => 09/477094 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3187 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684321.pdf [firstpage_image] =>[orig_patent_app_number] => 09477094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1401398 [patent_doc_number] => 06564315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction' [patent_app_type] => B1 [patent_app_number] => 09/476322 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 22439 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564315.pdf [firstpage_image] =>[orig_patent_app_number] => 09476322 [rel_patent_id] =>[rel_patent_doc_number] =>)