Eliseo Ramos Feliciano

Array ( [id] => 1421364 [patent_doc_number] => 06542984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Scheduler capable of issuing and reissuing dependency chains' [patent_app_type] => B1 [patent_app_number] => 09/476578 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 22299 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542984.pdf [firstpage_image] =>[orig_patent_app_number] => 09476578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1314551 [patent_doc_number] => 06622235 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Scheduler which retries load/store hit situations' [patent_app_type] => B1 [patent_app_number] => 09/476204 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 22743 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622235.pdf [firstpage_image] =>[orig_patent_app_number] => 09476204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1521763 [patent_doc_number] => 06502185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Pipeline elements which verify predecode information' [patent_app_type] => B1 [patent_app_number] => 09/476936 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 17212 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502185.pdf [firstpage_image] =>[orig_patent_app_number] => 09476936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7633061 [patent_doc_number] => 06658559 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method and apparatus for advancing load operations' [patent_app_type] => B1 [patent_app_number] => 09/476607 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7322 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658559.pdf [firstpage_image] =>[orig_patent_app_number] => 09476607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1365496 [patent_doc_number] => 06581154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Expanding microcode associated with full and partial width macroinstructions' [patent_app_type] => B1 [patent_app_number] => 09/476660 [patent_app_country] => US [patent_app_date] => 1999-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2723 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581154.pdf [firstpage_image] =>[orig_patent_app_number] => 09476660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1432397 [patent_doc_number] => 06505289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Apparatus and method for interconnecting 3-link nodes and parallel processing apparatus using the same' [patent_app_type] => B1 [patent_app_number] => 09/475049 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2726 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505289.pdf [firstpage_image] =>[orig_patent_app_number] => 09475049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1308650 [patent_doc_number] => 06629192 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method and apparatus for use of a non-volatile storage management system for PC/AT compatible system firmware' [patent_app_type] => B1 [patent_app_number] => 09/476434 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2753 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629192.pdf [firstpage_image] =>[orig_patent_app_number] => 09476434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431916 [patent_doc_number] => 06516405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method and system for safe data dependency collapsing based on control-flow speculation' [patent_app_type] => B1 [patent_app_number] => 09/475646 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8911 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516405.pdf [firstpage_image] =>[orig_patent_app_number] => 09475646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 568582 [patent_doc_number] => 07171547 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-30 [patent_title] => 'Method and apparatus to save processor architectural state for later process resumption' [patent_app_type] => utility [patent_app_number] => 09/473448 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5510 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/171/07171547.pdf [firstpage_image] =>[orig_patent_app_number] => 09473448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4420769 [patent_doc_number] => 06272453 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Concurrent legacy and native code execution techniques' [patent_app_type] => 1 [patent_app_number] => 9/451156 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3231 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272453.pdf [firstpage_image] =>[orig_patent_app_number] => 451156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4310312 [patent_doc_number] => 06212614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Legacy MIL-STD-1750A software emulator address translation using power PC memory management hardware' [patent_app_type] => 1 [patent_app_number] => 9/451431 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 6682 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212614.pdf [firstpage_image] =>[orig_patent_app_number] => 451431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1538905 [patent_doc_number] => 06412002 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method and apparatus for selecting nodes in configuring massively parallel systems' [patent_app_type] => B1 [patent_app_number] => 09/440807 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 33 [patent_no_of_words] => 12087 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412002.pdf [firstpage_image] =>[orig_patent_app_number] => 09440807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1411263 [patent_doc_number] => 06553442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Bus master for SMP execution of global operations utilizing a single token with implied release' [patent_app_type] => B1 [patent_app_number] => 09/435925 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6725 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553442.pdf [firstpage_image] =>[orig_patent_app_number] => 09435925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1421384 [patent_doc_number] => 06542986 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Resolving dependencies among concurrently dispatched instructions in a superscalar microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/437086 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8270 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542986.pdf [firstpage_image] =>[orig_patent_app_number] => 09437086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1298186 [patent_doc_number] => 06631463 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method and apparatus for patching problematic instructions in a microprocessor using software interrupts' [patent_app_type] => B1 [patent_app_number] => 09/436103 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4605 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631463.pdf [firstpage_image] =>[orig_patent_app_number] => 09436103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418993 [patent_doc_number] => 06546481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Split history tables for branch prediction' [patent_app_type] => B1 [patent_app_number] => 09/434096 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10307 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546481.pdf [firstpage_image] =>[orig_patent_app_number] => 09434096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1411860 [patent_doc_number] => 06553480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'System and method for managing the execution of instruction groups having multiple executable instructions' [patent_app_type] => B1 [patent_app_number] => 09/434095 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5696 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553480.pdf [firstpage_image] =>[orig_patent_app_number] => 09434095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416004 [patent_doc_number] => 06550004 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Hybrid branch predictor with improved selector table update mechanism' [patent_app_type] => B1 [patent_app_number] => 09/434984 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 10 [patent_no_of_words] => 8366 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/550/06550004.pdf [firstpage_image] =>[orig_patent_app_number] => 09434984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1415980 [patent_doc_number] => 06550002 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method and system for detecting a flush of an instruction without a flush indicator' [patent_app_type] => B1 [patent_app_number] => 09/435067 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6535 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/550/06550002.pdf [firstpage_image] =>[orig_patent_app_number] => 09435067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1381907 [patent_doc_number] => 06574727 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Method and apparatus for instruction sampling for performance monitoring and debug' [patent_app_type] => B1 [patent_app_number] => 09/435069 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7243 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574727.pdf [firstpage_image] =>[orig_patent_app_number] => 09435069 [rel_patent_id] =>[rel_patent_doc_number] =>)