
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1139090
[patent_doc_number] => 06789181
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-07
[patent_title] => 'Safety net paradigm for managing two computer execution modes'
[patent_app_type] => B1
[patent_app_number] => 09/432753
[patent_app_country] => US
[patent_app_date] => 1999-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 50
[patent_no_of_words] => 62265
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/789/06789181.pdf
[firstpage_image] =>[orig_patent_app_number] => 09432753
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/432753 | Safety net paradigm for managing two computer execution modes | Nov 2, 1999 | Issued |
Array
(
[id] => 1460076
[patent_doc_number] => 06463526
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-08
[patent_title] => 'Supporting multi-dimensional space-time computing through object versioning'
[patent_app_type] => B1
[patent_app_number] => 09/420335
[patent_app_country] => US
[patent_app_date] => 1999-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 25
[patent_no_of_words] => 6756
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/463/06463526.pdf
[firstpage_image] =>[orig_patent_app_number] => 09420335
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/420335 | Supporting multi-dimensional space-time computing through object versioning | Oct 17, 1999 | Issued |
Array
(
[id] => 1417065
[patent_doc_number] => 06532532
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-11
[patent_title] => 'Instruction execution mechanism'
[patent_app_type] => B1
[patent_app_number] => 09/419208
[patent_app_country] => US
[patent_app_date] => 1999-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2063
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/532/06532532.pdf
[firstpage_image] =>[orig_patent_app_number] => 09419208
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/419208 | Instruction execution mechanism | Oct 14, 1999 | Issued |
Array
(
[id] => 1289265
[patent_doc_number] => 06647490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-11
[patent_title] => 'Training line predictor for branch targets'
[patent_app_type] => B2
[patent_app_number] => 09/419832
[patent_app_country] => US
[patent_app_date] => 1999-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 24
[patent_no_of_words] => 21263
[patent_no_of_claims] => 49
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/647/06647490.pdf
[firstpage_image] =>[orig_patent_app_number] => 09419832
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/419832 | Training line predictor for branch targets | Oct 13, 1999 | Issued |
Array
(
[id] => 1417032
[patent_doc_number] => 06532530
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-11
[patent_title] => 'Data processing system and method for performing enhanced pipelined operations on instructions for normal and specific functions'
[patent_app_type] => B1
[patent_app_number] => 09/417667
[patent_app_country] => US
[patent_app_date] => 1999-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 7667
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/532/06532530.pdf
[firstpage_image] =>[orig_patent_app_number] => 09417667
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/417667 | Data processing system and method for performing enhanced pipelined operations on instructions for normal and specific functions | Oct 13, 1999 | Issued |
Array
(
[id] => 1506008
[patent_doc_number] => 06487652
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-26
[patent_title] => 'Method and apparatus for speculatively locking objects in an object-based system'
[patent_app_type] => B1
[patent_app_number] => 09/409932
[patent_app_country] => US
[patent_app_date] => 1999-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8254
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/487/06487652.pdf
[firstpage_image] =>[orig_patent_app_number] => 09409932
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/409932 | Method and apparatus for speculatively locking objects in an object-based system | Sep 29, 1999 | Issued |
Array
(
[id] => 7645886
[patent_doc_number] => 06477637
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Method and apparatus for transporting store requests between functional units within a processor'
[patent_app_type] => B1
[patent_app_number] => 09/409802
[patent_app_country] => US
[patent_app_date] => 1999-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2620
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 6
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/477/06477637.pdf
[firstpage_image] =>[orig_patent_app_number] => 09409802
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/409802 | Method and apparatus for transporting store requests between functional units within a processor | Sep 29, 1999 | Issued |
Array
(
[id] => 1501599
[patent_doc_number] => 06405303
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Massively parallel decoding and execution of variable-length instructions'
[patent_app_type] => B1
[patent_app_number] => 09/388211
[patent_app_country] => US
[patent_app_date] => 1999-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6616
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/405/06405303.pdf
[firstpage_image] =>[orig_patent_app_number] => 09388211
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/388211 | Massively parallel decoding and execution of variable-length instructions | Aug 30, 1999 | Issued |
Array
(
[id] => 1429077
[patent_doc_number] => 06513109
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-28
[patent_title] => 'Method and apparatus for implementing execution predicates in a computer processing system'
[patent_app_type] => B1
[patent_app_number] => 09/387220
[patent_app_country] => US
[patent_app_date] => 1999-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 12792
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/513/06513109.pdf
[firstpage_image] =>[orig_patent_app_number] => 09387220
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/387220 | Method and apparatus for implementing execution predicates in a computer processing system | Aug 30, 1999 | Issued |
Array
(
[id] => 1260492
[patent_doc_number] => 06668317
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-12-23
[patent_title] => 'Microengine for parallel processor architecture'
[patent_app_type] => B1
[patent_app_number] => 09/387046
[patent_app_country] => US
[patent_app_date] => 1999-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 11195
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/668/06668317.pdf
[firstpage_image] =>[orig_patent_app_number] => 09387046
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/387046 | Microengine for parallel processor architecture | Aug 30, 1999 | Issued |
Array
(
[id] => 1472003
[patent_doc_number] => 06460132
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Massively parallel instruction predecoding'
[patent_app_type] => B1
[patent_app_number] => 09/387024
[patent_app_country] => US
[patent_app_date] => 1999-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7356
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/460/06460132.pdf
[firstpage_image] =>[orig_patent_app_number] => 09387024
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/387024 | Massively parallel instruction predecoding | Aug 30, 1999 | Issued |
Array
(
[id] => 1243163
[patent_doc_number] => 06684322
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-27
[patent_title] => 'Method and system for instruction length decode'
[patent_app_type] => B1
[patent_app_number] => 09/385922
[patent_app_country] => US
[patent_app_date] => 1999-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 4428
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/684/06684322.pdf
[firstpage_image] =>[orig_patent_app_number] => 09385922
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/385922 | Method and system for instruction length decode | Aug 29, 1999 | Issued |
Array
(
[id] => 1425360
[patent_doc_number] => 06535973
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-18
[patent_title] => 'Method and system for speculatively issuing instructions'
[patent_app_type] => B1
[patent_app_number] => 09/383606
[patent_app_country] => US
[patent_app_date] => 1999-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4872
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/535/06535973.pdf
[firstpage_image] =>[orig_patent_app_number] => 09383606
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/383606 | Method and system for speculatively issuing instructions | Aug 25, 1999 | Issued |
Array
(
[id] => 1460070
[patent_doc_number] => 06463524
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-08
[patent_title] => 'Superscalar processor and method for incrementally issuing store instructions'
[patent_app_type] => B1
[patent_app_number] => 09/383607
[patent_app_country] => US
[patent_app_date] => 1999-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4417
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/463/06463524.pdf
[firstpage_image] =>[orig_patent_app_number] => 09383607
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/383607 | Superscalar processor and method for incrementally issuing store instructions | Aug 25, 1999 | Issued |
Array
(
[id] => 1506011
[patent_doc_number] => 06487653
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-26
[patent_title] => 'Method and apparatus for denormal load handling'
[patent_app_type] => B1
[patent_app_number] => 09/383138
[patent_app_country] => US
[patent_app_date] => 1999-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 12469
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/487/06487653.pdf
[firstpage_image] =>[orig_patent_app_number] => 09383138
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/383138 | Method and apparatus for denormal load handling | Aug 24, 1999 | Issued |
Array
(
[id] => 1365510
[patent_doc_number] => 06581155
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-17
[patent_title] => 'Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same'
[patent_app_type] => B1
[patent_app_number] => 09/382898
[patent_app_country] => US
[patent_app_date] => 1999-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4463
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/581/06581155.pdf
[firstpage_image] =>[orig_patent_app_number] => 09382898
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/382898 | Pipelined, superscalar floating point unit having out-of-order execution capability and processor employing the same | Aug 24, 1999 | Issued |
Array
(
[id] => 1444120
[patent_doc_number] => 06496919
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-17
[patent_title] => 'Data processor'
[patent_app_type] => B1
[patent_app_number] => 09/382598
[patent_app_country] => US
[patent_app_date] => 1999-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8042
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/496/06496919.pdf
[firstpage_image] =>[orig_patent_app_number] => 09382598
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/382598 | Data processor | Aug 24, 1999 | Issued |
Array
(
[id] => 4350243
[patent_doc_number] => 06334137
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Method and system for controlling parallel execution of jobs'
[patent_app_type] => 1
[patent_app_number] => 9/382355
[patent_app_country] => US
[patent_app_date] => 1999-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 28
[patent_no_of_words] => 5562
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/334/06334137.pdf
[firstpage_image] =>[orig_patent_app_number] => 382355
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/382355 | Method and system for controlling parallel execution of jobs | Aug 23, 1999 | Issued |
Array
(
[id] => 1415210
[patent_doc_number] => 06549954
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Object oriented on-chip messaging'
[patent_app_type] => B1
[patent_app_number] => 09/378877
[patent_app_country] => US
[patent_app_date] => 1999-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 7001
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/549/06549954.pdf
[firstpage_image] =>[orig_patent_app_number] => 09378877
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/378877 | Object oriented on-chip messaging | Aug 22, 1999 | Issued |
Array
(
[id] => 1185896
[patent_doc_number] => 06745318
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-01
[patent_title] => 'Method and apparatus of configurable processing'
[patent_app_type] => B1
[patent_app_number] => 09/376830
[patent_app_country] => US
[patent_app_date] => 1999-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3486
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/745/06745318.pdf
[firstpage_image] =>[orig_patent_app_number] => 09376830
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/376830 | Method and apparatus of configurable processing | Aug 17, 1999 | Issued |