Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1513337 [patent_doc_number] => 06442679 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Apparatus and method for guard outcome prediction' [patent_app_type] => B1 [patent_app_number] => 09/375813 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6171 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442679.pdf [firstpage_image] =>[orig_patent_app_number] => 09375813 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375813
Apparatus and method for guard outcome prediction Aug 16, 1999 Issued
Array ( [id] => 1460071 [patent_doc_number] => 06463525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Merging single precision floating point operands' [patent_app_type] => B1 [patent_app_number] => 09/375700 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2928 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463525.pdf [firstpage_image] =>[orig_patent_app_number] => 09375700 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375700
Merging single precision floating point operands Aug 15, 1999 Issued
Array ( [id] => 7634975 [patent_doc_number] => 06381691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method and apparatus for reordering memory operations along multiple execution paths in a processor' [patent_app_type] => B1 [patent_app_number] => 09/374255 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9530 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381691.pdf [firstpage_image] =>[orig_patent_app_number] => 09374255 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/374255
Method and apparatus for reordering memory operations along multiple execution paths in a processor Aug 12, 1999 Issued
Array ( [id] => 1197022 [patent_doc_number] => 06732259 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Processor having a conditional branch extension of an instruction set architecture' [patent_app_type] => B1 [patent_app_number] => 09/364789 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 22084 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732259.pdf [firstpage_image] =>[orig_patent_app_number] => 09364789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364789
Processor having a conditional branch extension of an instruction set architecture Jul 29, 1999 Issued
Array ( [id] => 1431914 [patent_doc_number] => 06516404 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Data processing system having hashed architected processor facilities' [patent_app_type] => B1 [patent_app_number] => 09/364283 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516404.pdf [firstpage_image] =>[orig_patent_app_number] => 09364283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364283
Data processing system having hashed architected processor facilities Jul 29, 1999 Issued
Array ( [id] => 4110182 [patent_doc_number] => 06134646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'System and method for executing and completing store instructions' [patent_app_type] => 1 [patent_app_number] => 9/364012 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3828 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134646.pdf [firstpage_image] =>[orig_patent_app_number] => 364012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364012
System and method for executing and completing store instructions Jul 28, 1999 Issued
Array ( [id] => 1460066 [patent_doc_number] => 06463523 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method and apparatus for delaying the execution of dependent loads' [patent_app_type] => B1 [patent_app_number] => 09/364245 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3720 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463523.pdf [firstpage_image] =>[orig_patent_app_number] => 09364245 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364245
Method and apparatus for delaying the execution of dependent loads Jul 28, 1999 Issued
Array ( [id] => 1415940 [patent_doc_number] => 06550000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Processor to execute in parallel plurality of instructions using plurality of functional units, and instruction allocation controller' [patent_app_type] => B1 [patent_app_number] => 09/362564 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 48 [patent_no_of_words] => 15880 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/550/06550000.pdf [firstpage_image] =>[orig_patent_app_number] => 09362564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362564
Processor to execute in parallel plurality of instructions using plurality of functional units, and instruction allocation controller Jul 27, 1999 Issued
Array ( [id] => 7638600 [patent_doc_number] => 06397321 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Digital signal processor' [patent_app_type] => B1 [patent_app_number] => 09/362950 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4984 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397321.pdf [firstpage_image] =>[orig_patent_app_number] => 09362950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362950
Digital signal processor Jul 27, 1999 Issued
Array ( [id] => 1587493 [patent_doc_number] => 06425075 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Branch prediction device with two levels of branch prediction cache' [patent_app_type] => B1 [patent_app_number] => 09/361809 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9637 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425075.pdf [firstpage_image] =>[orig_patent_app_number] => 09361809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361809
Branch prediction device with two levels of branch prediction cache Jul 26, 1999 Issued
Array ( [id] => 1311448 [patent_doc_number] => 06625721 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Registers for 2-D matrix processing' [patent_app_type] => B1 [patent_app_number] => 09/360612 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2301 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625721.pdf [firstpage_image] =>[orig_patent_app_number] => 09360612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360612
Registers for 2-D matrix processing Jul 25, 1999 Issued
Array ( [id] => 1595955 [patent_doc_number] => 06484253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Data processor' [patent_app_type] => B1 [patent_app_number] => 09/355024 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 56 [patent_no_of_words] => 31930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484253.pdf [firstpage_image] =>[orig_patent_app_number] => 09355024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/355024
Data processor Jul 22, 1999 Issued
Array ( [id] => 1456811 [patent_doc_number] => 06457119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Processor instruction pipeline with error detection scheme' [patent_app_type] => B1 [patent_app_number] => 09/360192 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4453 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457119.pdf [firstpage_image] =>[orig_patent_app_number] => 09360192 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360192
Processor instruction pipeline with error detection scheme Jul 22, 1999 Issued
Array ( [id] => 1431313 [patent_doc_number] => 06523110 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Decoupled fetch-execute engine with static branch prediction support' [patent_app_type] => B1 [patent_app_number] => 09/360054 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8785 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523110.pdf [firstpage_image] =>[orig_patent_app_number] => 09360054 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360054
Decoupled fetch-execute engine with static branch prediction support Jul 22, 1999 Issued
Array ( [id] => 1549640 [patent_doc_number] => 06374345 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Apparatus and method for handling tiny numbers using a super sticky bit in a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/359919 [patent_app_country] => US [patent_app_date] => 1999-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 13752 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374345.pdf [firstpage_image] =>[orig_patent_app_number] => 09359919 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359919
Apparatus and method for handling tiny numbers using a super sticky bit in a microprocessor Jul 21, 1999 Issued
Array ( [id] => 1568699 [patent_doc_number] => 06339823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method and apparatus for selective writing of incoherent MMX registers' [patent_app_type] => B1 [patent_app_number] => 09/357419 [patent_app_country] => US [patent_app_date] => 1999-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5094 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339823.pdf [firstpage_image] =>[orig_patent_app_number] => 09357419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/357419
Method and apparatus for selective writing of incoherent MMX registers Jul 19, 1999 Issued
Array ( [id] => 4199527 [patent_doc_number] => 06038674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system' [patent_app_type] => 1 [patent_app_number] => 9/352343 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 24877 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038674.pdf [firstpage_image] =>[orig_patent_app_number] => 352343 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/352343
Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system Jul 12, 1999 Issued
Array ( [id] => 1602053 [patent_doc_number] => 06385716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method and apparatus for tracking coherence of dual floating point and MMX register files' [patent_app_type] => B1 [patent_app_number] => 09/349441 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3760 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385716.pdf [firstpage_image] =>[orig_patent_app_number] => 09349441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/349441
Method and apparatus for tracking coherence of dual floating point and MMX register files Jul 8, 1999 Issued
Array ( [id] => 1524944 [patent_doc_number] => 06415378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method and system for tracking the progress of an instruction in an out-of-order processor' [patent_app_type] => B1 [patent_app_number] => 09/343359 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4228 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415378.pdf [firstpage_image] =>[orig_patent_app_number] => 09343359 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343359
Method and system for tracking the progress of an instruction in an out-of-order processor Jun 29, 1999 Issued
Array ( [id] => 4350796 [patent_doc_number] => 06321380 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method and apparatus for modifying instruction operations in a processor' [patent_app_type] => 1 [patent_app_number] => 9/345161 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3807 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321380.pdf [firstpage_image] =>[orig_patent_app_number] => 345161 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345161
Method and apparatus for modifying instruction operations in a processor Jun 28, 1999 Issued
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