Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 789414 [patent_doc_number] => 06988183 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-17 [patent_title] => 'Methods for increasing instruction-level parallelism in microprocessors and digital system' [patent_app_type] => utility [patent_app_number] => 09/340172 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 18068 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/988/06988183.pdf [firstpage_image] =>[orig_patent_app_number] => 09340172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/340172
Methods for increasing instruction-level parallelism in microprocessors and digital system Jun 24, 1999 Issued
Array ( [id] => 7638601 [patent_doc_number] => 06397320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method for just-in-time delivery of load data via cycle of dependency' [patent_app_type] => B1 [patent_app_number] => 09/344061 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7729 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397320.pdf [firstpage_image] =>[orig_patent_app_number] => 09344061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344061
Method for just-in-time delivery of load data via cycle of dependency Jun 24, 1999 Issued
Array ( [id] => 1462465 [patent_doc_number] => 06427204 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method for just in-time delivery of instructions in a data processing system' [patent_app_type] => B1 [patent_app_number] => 09/344058 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7951 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427204.pdf [firstpage_image] =>[orig_patent_app_number] => 09344058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344058
Method for just in-time delivery of instructions in a data processing system Jun 24, 1999 Issued
Array ( [id] => 1481155 [patent_doc_number] => 06389529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method for alternate preferred time delivery of load data' [patent_app_type] => B1 [patent_app_number] => 09/344059 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7744 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389529.pdf [firstpage_image] =>[orig_patent_app_number] => 09344059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344059
Method for alternate preferred time delivery of load data Jun 24, 1999 Issued
Array ( [id] => 1513333 [patent_doc_number] => 06442677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Apparatus and method for superforwarding load operands in a microprocessor' [patent_app_type] => B1 [patent_app_number] => 09/329497 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 15247 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442677.pdf [firstpage_image] =>[orig_patent_app_number] => 09329497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/329497
Apparatus and method for superforwarding load operands in a microprocessor Jun 9, 1999 Issued
09/327211 MECHANISM FOR SOFTWARE PIPELINING LOOP NESTS Jun 6, 1999 Abandoned
Array ( [id] => 1472007 [patent_doc_number] => 06460133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Queue resource tracking in a multiprocessor system' [patent_app_type] => B1 [patent_app_number] => 09/315488 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460133.pdf [firstpage_image] =>[orig_patent_app_number] => 09315488 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315488
Queue resource tracking in a multiprocessor system May 19, 1999 Issued
Array ( [id] => 1421436 [patent_doc_number] => 06542991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Multiple-thread processor with single-thread interface shared among threads' [patent_app_type] => B1 [patent_app_number] => 09/309734 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 18262 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542991.pdf [firstpage_image] =>[orig_patent_app_number] => 09309734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/309734
Multiple-thread processor with single-thread interface shared among threads May 10, 1999 Issued
Array ( [id] => 1385589 [patent_doc_number] => 06571301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Multi processor system and FIFO circuit' [patent_app_type] => B1 [patent_app_number] => 09/304842 [patent_app_country] => US [patent_app_date] => 1999-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 11917 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571301.pdf [firstpage_image] =>[orig_patent_app_number] => 09304842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304842
Multi processor system and FIFO circuit May 4, 1999 Issued
Array ( [id] => 1481623 [patent_doc_number] => 06345317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Information processing system having a plurality of input/output devices and a plurality of processors' [patent_app_type] => B1 [patent_app_number] => 09/305983 [patent_app_country] => US [patent_app_date] => 1999-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 29 [patent_no_of_words] => 6149 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345317.pdf [firstpage_image] =>[orig_patent_app_number] => 09305983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/305983
Information processing system having a plurality of input/output devices and a plurality of processors May 4, 1999 Issued
Array ( [id] => 1462458 [patent_doc_number] => 06427202 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Microcontroller with configurable instruction set' [patent_app_type] => B1 [patent_app_number] => 09/304745 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4589 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427202.pdf [firstpage_image] =>[orig_patent_app_number] => 09304745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304745
Microcontroller with configurable instruction set May 3, 1999 Issued
Array ( [id] => 1587480 [patent_doc_number] => 06425071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Subsystem bridge of AMBA\'s ASB bus to peripheral component interconnect (PCI) bus' [patent_app_type] => B1 [patent_app_number] => 09/303890 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2523 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425071.pdf [firstpage_image] =>[orig_patent_app_number] => 09303890 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303890
Subsystem bridge of AMBA's ASB bus to peripheral component interconnect (PCI) bus May 2, 1999 Issued
Array ( [id] => 4381384 [patent_doc_number] => 06256719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Message-routing protocol for arbitrarily connected processors frankel' [patent_app_type] => 1 [patent_app_number] => 9/298376 [patent_app_country] => US [patent_app_date] => 1999-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5349 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256719.pdf [firstpage_image] =>[orig_patent_app_number] => 298376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298376
Message-routing protocol for arbitrarily connected processors frankel Apr 22, 1999 Issued
Array ( [id] => 4424592 [patent_doc_number] => 06266760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Intermediate-grain reconfigurable processing device' [patent_app_type] => 1 [patent_app_number] => 9/292497 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 38 [patent_no_of_words] => 15263 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266760.pdf [firstpage_image] =>[orig_patent_app_number] => 292497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292497
Intermediate-grain reconfigurable processing device Apr 14, 1999 Issued
Array ( [id] => 1557331 [patent_doc_number] => 06349378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Data processing using various data processors' [patent_app_type] => B1 [patent_app_number] => 09/282325 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5936 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349378.pdf [firstpage_image] =>[orig_patent_app_number] => 09282325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282325
Data processing using various data processors Mar 30, 1999 Issued
Array ( [id] => 1471996 [patent_doc_number] => 06460130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Detecting full conditions in a queue' [patent_app_type] => B1 [patent_app_number] => 09/281079 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 37 [patent_no_of_words] => 19506 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460130.pdf [firstpage_image] =>[orig_patent_app_number] => 09281079 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/281079
Detecting full conditions in a queue Mar 29, 1999 Issued
Array ( [id] => 1221741 [patent_doc_number] => 06708268 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Microcontroller instruction set' [patent_app_type] => B1 [patent_app_number] => 09/280112 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 95 [patent_figures_cnt] => 114 [patent_no_of_words] => 11904 [patent_no_of_claims] => 142 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708268.pdf [firstpage_image] =>[orig_patent_app_number] => 09280112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280112
Microcontroller instruction set Mar 25, 1999 Issued
Array ( [id] => 4422402 [patent_doc_number] => 06233675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Facility to allow fast execution of and, or, and test instructions' [patent_app_type] => 1 [patent_app_number] => 9/276315 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5058 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233675.pdf [firstpage_image] =>[orig_patent_app_number] => 276315 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276315
Facility to allow fast execution of and, or, and test instructions Mar 24, 1999 Issued
Array ( [id] => 4273741 [patent_doc_number] => 06209078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Accelerated multimedia processor' [patent_app_type] => 1 [patent_app_number] => 9/276262 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4181 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209078.pdf [firstpage_image] =>[orig_patent_app_number] => 276262 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276262
Accelerated multimedia processor Mar 24, 1999 Issued
Array ( [id] => 4400442 [patent_doc_number] => 06304956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Using two barrel shifters to implement shift, rotate, rotate with carry, and shift double as specified by the X86 architecture' [patent_app_type] => 1 [patent_app_number] => 9/276427 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7971 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304956.pdf [firstpage_image] =>[orig_patent_app_number] => 276427 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276427
Using two barrel shifters to implement shift, rotate, rotate with carry, and shift double as specified by the X86 architecture Mar 24, 1999 Issued
Menu