
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 789414
[patent_doc_number] => 06988183
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-01-17
[patent_title] => 'Methods for increasing instruction-level parallelism in microprocessors and digital system'
[patent_app_type] => utility
[patent_app_number] => 09/340172
[patent_app_country] => US
[patent_app_date] => 1999-06-25
[patent_effective_date] => 0000-00-00
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/988/06988183.pdf
[firstpage_image] =>[orig_patent_app_number] => 09340172
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/340172 | Methods for increasing instruction-level parallelism in microprocessors and digital system | Jun 24, 1999 | Issued |
Array
(
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[patent_doc_number] => 06397320
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[patent_kind] => B1
[patent_issue_date] => 2002-05-28
[patent_title] => 'Method for just-in-time delivery of load data via cycle of dependency'
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[patent_app_number] => 09/344061
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Array
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[patent_doc_number] => 06427204
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[patent_issue_date] => 2002-07-30
[patent_title] => 'Method for just in-time delivery of instructions in a data processing system'
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Array
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[patent_doc_number] => 06389529
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[patent_issue_date] => 2002-05-14
[patent_title] => 'Method for alternate preferred time delivery of load data'
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[patent_app_date] => 1999-06-25
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Array
(
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[patent_doc_number] => 06442677
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[patent_issue_date] => 2002-08-27
[patent_title] => 'Apparatus and method for superforwarding load operands in a microprocessor'
[patent_app_type] => B1
[patent_app_number] => 09/329497
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/329497 | Apparatus and method for superforwarding load operands in a microprocessor | Jun 9, 1999 | Issued |
| 09/327211 | MECHANISM FOR SOFTWARE PIPELINING LOOP NESTS | Jun 6, 1999 | Abandoned |
Array
(
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[patent_doc_number] => 06460133
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[patent_title] => 'Queue resource tracking in a multiprocessor system'
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Array
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[patent_title] => 'Multiple-thread processor with single-thread interface shared among threads'
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Array
(
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[patent_issue_date] => 2003-05-27
[patent_title] => 'Multi processor system and FIFO circuit'
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[patent_app_number] => 09/304842
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Array
(
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[patent_title] => 'Information processing system having a plurality of input/output devices and a plurality of processors'
[patent_app_type] => B1
[patent_app_number] => 09/305983
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Array
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[patent_title] => 'Microcontroller with configurable instruction set'
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[patent_app_number] => 09/304745
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Array
(
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[patent_title] => 'Subsystem bridge of AMBA\'s ASB bus to peripheral component interconnect (PCI) bus'
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Array
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[patent_title] => 'Message-routing protocol for arbitrarily connected processors frankel'
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Array
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Array
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Array
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Array
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Array
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Array
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