Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4350010 [patent_doc_number] => 06321328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Processor having data buffer for speculative loads' [patent_app_type] => 1 [patent_app_number] => 9/274166 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4280 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321328.pdf [firstpage_image] =>[orig_patent_app_number] => 274166 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/274166
Processor having data buffer for speculative loads Mar 21, 1999 Issued
Array ( [id] => 4280210 [patent_doc_number] => 06205546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Computer system having a multi-pointer branch instruction and method' [patent_app_type] => 1 [patent_app_number] => 9/273386 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5606 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205546.pdf [firstpage_image] =>[orig_patent_app_number] => 273386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273386
Computer system having a multi-pointer branch instruction and method Mar 21, 1999 Issued
Array ( [id] => 4373924 [patent_doc_number] => 06202144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Computer system having a single pointer branch instruction and method' [patent_app_type] => 1 [patent_app_number] => 9/273369 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4118 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202144.pdf [firstpage_image] =>[orig_patent_app_number] => 273369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/273369
Computer system having a single pointer branch instruction and method Mar 21, 1999 Issued
Array ( [id] => 4298150 [patent_doc_number] => 06282585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Cooperative interconnection for reducing port pressure in clustered microprocessors' [patent_app_type] => 1 [patent_app_number] => 9/274134 [patent_app_country] => US [patent_app_date] => 1999-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8600 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282585.pdf [firstpage_image] =>[orig_patent_app_number] => 274134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/274134
Cooperative interconnection for reducing port pressure in clustered microprocessors Mar 21, 1999 Issued
Array ( [id] => 1573808 [patent_doc_number] => 06499101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Static branch prediction mechanism for conditional branch instructions' [patent_app_type] => B1 [patent_app_number] => 09/272225 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10716 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499101.pdf [firstpage_image] =>[orig_patent_app_number] => 09272225 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/272225
Static branch prediction mechanism for conditional branch instructions Mar 17, 1999 Issued
Array ( [id] => 1456828 [patent_doc_number] => 06457121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and apparatus for reordering data in X86 ordering' [patent_app_type] => B1 [patent_app_number] => 09/270981 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4792 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457121.pdf [firstpage_image] =>[orig_patent_app_number] => 09270981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270981
Method and apparatus for reordering data in X86 ordering Mar 16, 1999 Issued
Array ( [id] => 4351797 [patent_doc_number] => 06314491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Peer-to-peer cache moves in a multiprocessor data processing system' [patent_app_type] => 1 [patent_app_number] => 9/259950 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 12200 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314491.pdf [firstpage_image] =>[orig_patent_app_number] => 259950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259950
Peer-to-peer cache moves in a multiprocessor data processing system Feb 28, 1999 Issued
Array ( [id] => 4260196 [patent_doc_number] => 06092177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Computer architecture capable of execution of general purpose multiple instructions' [patent_app_type] => 1 [patent_app_number] => 9/257883 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 7405 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092177.pdf [firstpage_image] =>[orig_patent_app_number] => 257883 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/257883
Computer architecture capable of execution of general purpose multiple instructions Feb 24, 1999 Issued
Array ( [id] => 4292455 [patent_doc_number] => 06247114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Rapid selection of oldest eligible entry in a queue' [patent_app_type] => 1 [patent_app_number] => 9/253478 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 37 [patent_no_of_words] => 19300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247114.pdf [firstpage_image] =>[orig_patent_app_number] => 253478 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253478
Rapid selection of oldest eligible entry in a queue Feb 18, 1999 Issued
Array ( [id] => 4317926 [patent_doc_number] => 06185672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method and apparatus for instruction queue compression' [patent_app_type] => 1 [patent_app_number] => 9/253466 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 37 [patent_no_of_words] => 19227 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185672.pdf [firstpage_image] =>[orig_patent_app_number] => 253466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253466
Method and apparatus for instruction queue compression Feb 18, 1999 Issued
09/249498 PROCESSOR HAVING A CONDITIONAL BRANCH EXTENSION OF AN INSTRUCTION SET ARCHITECTURE Feb 11, 1999 Abandoned
Array ( [id] => 1485075 [patent_doc_number] => 06453407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Configurable long instruction word architecture and instruction set' [patent_app_type] => B1 [patent_app_number] => 09/247686 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8167 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453407.pdf [firstpage_image] =>[orig_patent_app_number] => 09247686 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/247686
Configurable long instruction word architecture and instruction set Feb 9, 1999 Issued
Array ( [id] => 4426931 [patent_doc_number] => 06195743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method and system for compressing reduced instruction set computer (RISC) executable code through instruction set expansion' [patent_app_type] => 1 [patent_app_number] => 9/239260 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195743.pdf [firstpage_image] =>[orig_patent_app_number] => 239260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/239260
Method and system for compressing reduced instruction set computer (RISC) executable code through instruction set expansion Jan 28, 1999 Issued
Array ( [id] => 4280159 [patent_doc_number] => 06205542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Processor pipeline including replay' [patent_app_type] => 1 [patent_app_number] => 9/231426 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4949 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205542.pdf [firstpage_image] =>[orig_patent_app_number] => 231426 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231426
Processor pipeline including replay Jan 13, 1999 Issued
Array ( [id] => 1549647 [patent_doc_number] => 06374347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Register file backup queue' [patent_app_type] => B1 [patent_app_number] => 09/229172 [patent_app_country] => US [patent_app_date] => 1999-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3609 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374347.pdf [firstpage_image] =>[orig_patent_app_number] => 09229172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229172
Register file backup queue Jan 12, 1999 Issued
Array ( [id] => 4325670 [patent_doc_number] => 06253305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Microprocessor for supporting reduction of program codes in size' [patent_app_type] => 1 [patent_app_number] => 9/226791 [patent_app_country] => US [patent_app_date] => 1999-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 14129 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253305.pdf [firstpage_image] =>[orig_patent_app_number] => 226791 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/226791
Microprocessor for supporting reduction of program codes in size Jan 6, 1999 Issued
Array ( [id] => 4424604 [patent_doc_number] => 06266763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values' [patent_app_type] => 1 [patent_app_number] => 9/225982 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12893 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266763.pdf [firstpage_image] =>[orig_patent_app_number] => 225982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225982
Physical rename register for efficiently storing floating point, integer, condition code, and multimedia values Jan 4, 1999 Issued
Array ( [id] => 4325648 [patent_doc_number] => 06253304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Collation of interrupt control devices' [patent_app_type] => 1 [patent_app_number] => 9/224821 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7538 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253304.pdf [firstpage_image] =>[orig_patent_app_number] => 224821 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224821
Collation of interrupt control devices Jan 3, 1999 Issued
Array ( [id] => 4292425 [patent_doc_number] => 06247112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Bit manipulation instructions' [patent_app_type] => 1 [patent_app_number] => 9/223105 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3386 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247112.pdf [firstpage_image] =>[orig_patent_app_number] => 223105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223105
Bit manipulation instructions Dec 29, 1998 Issued
Array ( [id] => 7642370 [patent_doc_number] => 06430676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method and system for calculating instruction lookahead' [patent_app_type] => B1 [patent_app_number] => 09/220969 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6341 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430676.pdf [firstpage_image] =>[orig_patent_app_number] => 09220969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/220969
Method and system for calculating instruction lookahead Dec 22, 1998 Issued
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