
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4350010
[patent_doc_number] => 06321328
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Processor having data buffer for speculative loads'
[patent_app_type] => 1
[patent_app_number] => 9/274166
[patent_app_country] => US
[patent_app_date] => 1999-03-22
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Array
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[patent_issue_date] => 2001-03-20
[patent_title] => 'Computer system having a multi-pointer branch instruction and method'
[patent_app_type] => 1
[patent_app_number] => 9/273386
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[patent_app_date] => 1999-03-22
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Array
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[patent_title] => 'Computer system having a single pointer branch instruction and method'
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Array
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[patent_issue_date] => 2001-08-28
[patent_title] => 'Cooperative interconnection for reducing port pressure in clustered microprocessors'
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[patent_app_number] => 9/274134
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Array
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Array
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[patent_title] => 'Method and apparatus for reordering data in X86 ordering'
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Array
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Array
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[patent_title] => 'Computer architecture capable of execution of general purpose multiple instructions'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/257883 | Computer architecture capable of execution of general purpose multiple instructions | Feb 24, 1999 | Issued |
Array
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Array
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| 09/249498 | PROCESSOR HAVING A CONDITIONAL BRANCH EXTENSION OF AN INSTRUCTION SET ARCHITECTURE | Feb 11, 1999 | Abandoned |
Array
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Array
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Array
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