Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4350856 [patent_doc_number] => 06334177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Method and system for supporting software partitions and dynamic reconfiguration within a non-uniform memory access system' [patent_app_type] => 1 [patent_app_number] => 9/216223 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3092 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/334/06334177.pdf [firstpage_image] =>[orig_patent_app_number] => 216223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/216223
Method and system for supporting software partitions and dynamic reconfiguration within a non-uniform memory access system Dec 17, 1998 Issued
Array ( [id] => 4269349 [patent_doc_number] => 06138228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Protocol and bus link system between components of a micro-controller' [patent_app_type] => 1 [patent_app_number] => 9/209997 [patent_app_country] => US [patent_app_date] => 1998-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 10046 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138228.pdf [firstpage_image] =>[orig_patent_app_number] => 209997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209997
Protocol and bus link system between components of a micro-controller Dec 10, 1998 Issued
Array ( [id] => 4312479 [patent_doc_number] => 06237085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Processor and method for generating less than (LT), Greater than (GT), and equal to (EQ) condition code bits concurrent with a logical or complex operation' [patent_app_type] => 1 [patent_app_number] => 9/207482 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237085.pdf [firstpage_image] =>[orig_patent_app_number] => 207482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207482
Processor and method for generating less than (LT), Greater than (GT), and equal to (EQ) condition code bits concurrent with a logical or complex operation Dec 7, 1998 Issued
Array ( [id] => 4402462 [patent_doc_number] => 06279100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Local stall control method and structure in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 9/204535 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 42 [patent_no_of_words] => 14741 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279100.pdf [firstpage_image] =>[orig_patent_app_number] => 204535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204535
Local stall control method and structure in a microprocessor Dec 2, 1998 Issued
Array ( [id] => 4280350 [patent_doc_number] => 06205556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Semiconductor integrated circuit device comprising a memory array and a processing circuit' [patent_app_type] => 1 [patent_app_number] => 9/198658 [patent_app_country] => US [patent_app_date] => 1998-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 54 [patent_no_of_words] => 24821 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205556.pdf [firstpage_image] =>[orig_patent_app_number] => 198658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/198658
Semiconductor integrated circuit device comprising a memory array and a processing circuit Nov 23, 1998 Issued
Array ( [id] => 1567409 [patent_doc_number] => 06363453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Parallel processor with redundancy of processor pairs' [patent_app_type] => B1 [patent_app_number] => 09/194459 [patent_app_country] => US [patent_app_date] => 1998-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 7303 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363453.pdf [firstpage_image] =>[orig_patent_app_number] => 09194459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/194459
Parallel processor with redundancy of processor pairs Nov 23, 1998 Issued
Array ( [id] => 4352122 [patent_doc_number] => 06314513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Method and apparatus for transferring data between a register stack and a memory resource' [patent_app_type] => 1 [patent_app_number] => 9/199003 [patent_app_country] => US [patent_app_date] => 1998-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13665 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314513.pdf [firstpage_image] =>[orig_patent_app_number] => 199003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/199003
Method and apparatus for transferring data between a register stack and a memory resource Nov 22, 1998 Issued
Array ( [id] => 4270464 [patent_doc_number] => 06223274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Power-and speed-efficient data storage/transfer architecture models and design methodologies for programmable or reusable multi-media processors' [patent_app_type] => 1 [patent_app_number] => 9/196645 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 17247 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223274.pdf [firstpage_image] =>[orig_patent_app_number] => 196645 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196645
Power-and speed-efficient data storage/transfer architecture models and design methodologies for programmable or reusable multi-media processors Nov 18, 1998 Issued
Array ( [id] => 4258643 [patent_doc_number] => 06145125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method and storage medium for building very large executable programs' [patent_app_type] => 1 [patent_app_number] => 9/190166 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2880 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145125.pdf [firstpage_image] =>[orig_patent_app_number] => 190166 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190166
Method and storage medium for building very large executable programs Nov 11, 1998 Issued
Array ( [id] => 4333346 [patent_doc_number] => 06332188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Digital signal processor with bit FIFO' [patent_app_type] => 1 [patent_app_number] => 9/187479 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5588 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/332/06332188.pdf [firstpage_image] =>[orig_patent_app_number] => 187479 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187479
Digital signal processor with bit FIFO Nov 5, 1998 Issued
Array ( [id] => 4204106 [patent_doc_number] => 06151668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication' [patent_app_type] => 1 [patent_app_number] => 9/187539 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8518 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151668.pdf [firstpage_image] =>[orig_patent_app_number] => 187539 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187539
Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication Nov 5, 1998 Issued
Array ( [id] => 4257827 [patent_doc_number] => 06145073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Data flow integrated circuit architecture' [patent_app_type] => 1 [patent_app_number] => 9/174439 [patent_app_country] => US [patent_app_date] => 1998-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 9029 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145073.pdf [firstpage_image] =>[orig_patent_app_number] => 174439 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/174439
Data flow integrated circuit architecture Oct 15, 1998 Issued
Array ( [id] => 4239194 [patent_doc_number] => 06088783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'DPS having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word' [patent_app_type] => 1 [patent_app_number] => 9/158208 [patent_app_country] => US [patent_app_date] => 1998-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 22007 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088783.pdf [firstpage_image] =>[orig_patent_app_number] => 158208 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158208
DPS having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word Sep 21, 1998 Issued
Array ( [id] => 4192714 [patent_doc_number] => 06141743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Token-based storage for general purpose processing' [patent_app_type] => 1 [patent_app_number] => 9/154689 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4971 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141743.pdf [firstpage_image] =>[orig_patent_app_number] => 154689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/154689
Token-based storage for general purpose processing Sep 16, 1998 Issued
Array ( [id] => 4260210 [patent_doc_number] => 06092178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'System for responding to a resource request' [patent_app_type] => 1 [patent_app_number] => 9/146771 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6235 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092178.pdf [firstpage_image] =>[orig_patent_app_number] => 146771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146771
System for responding to a resource request Sep 2, 1998 Issued
Array ( [id] => 4424825 [patent_doc_number] => 06230260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Circuit arrangement and method of speculative instruction execution utilizing instruction history caching' [patent_app_type] => 1 [patent_app_number] => 9/144664 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 12860 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230260.pdf [firstpage_image] =>[orig_patent_app_number] => 144664 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/144664
Circuit arrangement and method of speculative instruction execution utilizing instruction history caching Aug 31, 1998 Issued
Array ( [id] => 4237418 [patent_doc_number] => 06112289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 9/143530 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 78 [patent_figures_cnt] => 78 [patent_no_of_words] => 44863 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112289.pdf [firstpage_image] =>[orig_patent_app_number] => 143530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143530
Data processor Aug 27, 1998 Issued
Array ( [id] => 4374314 [patent_doc_number] => 06175911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method and apparatus for concurrently executing multiplication and iterative operations' [patent_app_type] => 1 [patent_app_number] => 9/137583 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 14447 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175911.pdf [firstpage_image] =>[orig_patent_app_number] => 137583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137583
Method and apparatus for concurrently executing multiplication and iterative operations Aug 20, 1998 Issued
Array ( [id] => 4156120 [patent_doc_number] => 06122723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Switching multi-initiator SCSI devices to a singular target bus' [patent_app_type] => 1 [patent_app_number] => 9/137082 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3261 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122723.pdf [firstpage_image] =>[orig_patent_app_number] => 137082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137082
Switching multi-initiator SCSI devices to a singular target bus Aug 19, 1998 Issued
Array ( [id] => 4318118 [patent_doc_number] => 06182209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Data processing device with relative jump instruction' [patent_app_type] => 1 [patent_app_number] => 9/135490 [patent_app_country] => US [patent_app_date] => 1998-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3074 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182209.pdf [firstpage_image] =>[orig_patent_app_number] => 135490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135490
Data processing device with relative jump instruction Aug 16, 1998 Issued
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