Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4235006 [patent_doc_number] => 06088511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Nested parallel 2D Delaunay triangulation method' [patent_app_type] => 1 [patent_app_number] => 9/108151 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 24071 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088511.pdf [firstpage_image] =>[orig_patent_app_number] => 108151 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108151
Nested parallel 2D Delaunay triangulation method Jun 29, 1998 Issued
Array ( [id] => 4124285 [patent_doc_number] => 06101599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'System for context switching between processing elements in a pipeline of processing elements' [patent_app_type] => 1 [patent_app_number] => 9/106244 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8000 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101599.pdf [firstpage_image] =>[orig_patent_app_number] => 106244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106244
System for context switching between processing elements in a pipeline of processing elements Jun 28, 1998 Issued
Array ( [id] => 4333705 [patent_doc_number] => 06243701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'System and method for sorting character strings containing accented and unaccented characters' [patent_app_type] => 1 [patent_app_number] => 9/107089 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243701.pdf [firstpage_image] =>[orig_patent_app_number] => 107089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/107089
System and method for sorting character strings containing accented and unaccented characters Jun 28, 1998 Issued
Array ( [id] => 4345733 [patent_doc_number] => 06330604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage' [patent_app_type] => 1 [patent_app_number] => 9/102812 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 23119 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330604.pdf [firstpage_image] =>[orig_patent_app_number] => 102812 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102812
Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage Jun 22, 1998 Issued
Array ( [id] => 4204310 [patent_doc_number] => 06151681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Dynamic device power management' [patent_app_type] => 1 [patent_app_number] => 9/102245 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1793 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151681.pdf [firstpage_image] =>[orig_patent_app_number] => 102245 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102245
Dynamic device power management Jun 21, 1998 Issued
Array ( [id] => 4374019 [patent_doc_number] => 06175892 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Registers and methods for accessing registers for use in a single instruction multiple data system' [patent_app_type] => 1 [patent_app_number] => 9/099989 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 7528 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175892.pdf [firstpage_image] =>[orig_patent_app_number] => 099989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/099989
Registers and methods for accessing registers for use in a single instruction multiple data system Jun 18, 1998 Issued
Array ( [id] => 1568538 [patent_doc_number] => 06339788 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method for encapsulating hardware to allow multi-tasking of microcode' [patent_app_type] => B1 [patent_app_number] => 09/097036 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3410 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339788.pdf [firstpage_image] =>[orig_patent_app_number] => 09097036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097036
Method for encapsulating hardware to allow multi-tasking of microcode Jun 11, 1998 Issued
09/086696 COMPRESSED INSTRUCTION FORMAT FOR USE IN A VLIW PROCESSOR AND PROCESSOR FOR PROCESSING SUCH INSTRUCTIONS May 28, 1998 Issued
Array ( [id] => 4422175 [patent_doc_number] => 06173344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'SCSI bus transceiver and method for making the same' [patent_app_type] => 1 [patent_app_number] => 9/085671 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4122 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173344.pdf [firstpage_image] =>[orig_patent_app_number] => 085671 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/085671
SCSI bus transceiver and method for making the same May 26, 1998 Issued
Array ( [id] => 4103885 [patent_doc_number] => 06026479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Apparatus and method for efficient switching of CPU mode between regions of high instruction level parallism and low instruction level parallism in computer programs' [patent_app_type] => 1 [patent_app_number] => 9/064701 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5603 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026479.pdf [firstpage_image] =>[orig_patent_app_number] => 064701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064701
Apparatus and method for efficient switching of CPU mode between regions of high instruction level parallism and low instruction level parallism in computer programs Apr 21, 1998 Issued
Array ( [id] => 4167477 [patent_doc_number] => 06065114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Cover instruction and asynchronous backing store switch' [patent_app_type] => 1 [patent_app_number] => 9/064091 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9784 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065114.pdf [firstpage_image] =>[orig_patent_app_number] => 064091 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064091
Cover instruction and asynchronous backing store switch Apr 20, 1998 Issued
Array ( [id] => 4239240 [patent_doc_number] => 06088785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method of configuring a functionally redefinable signal processing system' [patent_app_type] => 1 [patent_app_number] => 9/060747 [patent_app_country] => US [patent_app_date] => 1998-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 12309 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088785.pdf [firstpage_image] =>[orig_patent_app_number] => 060747 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/060747
Method of configuring a functionally redefinable signal processing system Apr 14, 1998 Issued
Array ( [id] => 4085355 [patent_doc_number] => 06009506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions' [patent_app_type] => 1 [patent_app_number] => 9/059271 [patent_app_country] => US [patent_app_date] => 1998-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 7402 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009506.pdf [firstpage_image] =>[orig_patent_app_number] => 059271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059271
Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions Apr 9, 1998 Issued
Array ( [id] => 4257089 [patent_doc_number] => 06081882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Quantum acceleration of conventional non-quantum computers' [patent_app_type] => 1 [patent_app_number] => 9/057701 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6632 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081882.pdf [firstpage_image] =>[orig_patent_app_number] => 057701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/057701
Quantum acceleration of conventional non-quantum computers Apr 8, 1998 Issued
Array ( [id] => 4310502 [patent_doc_number] => 06212628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Mesh connected computer' [patent_app_type] => 1 [patent_app_number] => 9/057481 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 75 [patent_no_of_words] => 67456 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212628.pdf [firstpage_image] =>[orig_patent_app_number] => 057481 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/057481
Mesh connected computer Apr 8, 1998 Issued
Array ( [id] => 4100534 [patent_doc_number] => 06055650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Processor configured to detect program phase changes and to adapt thereto' [patent_app_type] => 1 [patent_app_number] => 9/056005 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8390 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055650.pdf [firstpage_image] =>[orig_patent_app_number] => 056005 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056005
Processor configured to detect program phase changes and to adapt thereto Apr 5, 1998 Issued
Array ( [id] => 4260159 [patent_doc_number] => 06092175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Shared register storage mechanisms for multithreaded computer systems with out-of-order execution' [patent_app_type] => 1 [patent_app_number] => 9/053903 [patent_app_country] => US [patent_app_date] => 1998-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 44 [patent_no_of_words] => 10773 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092175.pdf [firstpage_image] =>[orig_patent_app_number] => 053903 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053903
Shared register storage mechanisms for multithreaded computer systems with out-of-order execution Apr 1, 1998 Issued
Array ( [id] => 1604404 [patent_doc_number] => 06434590 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Methods and apparatus for scheduling parallel processors' [patent_app_type] => B1 [patent_app_number] => 09/053873 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 15968 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434590.pdf [firstpage_image] =>[orig_patent_app_number] => 09053873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053873
Methods and apparatus for scheduling parallel processors Mar 31, 1998 Issued
Array ( [id] => 4156148 [patent_doc_number] => 06122725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Executing partial-width packed data instructions' [patent_app_type] => 1 [patent_app_number] => 9/053002 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 8785 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122725.pdf [firstpage_image] =>[orig_patent_app_number] => 053002 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053002
Executing partial-width packed data instructions Mar 30, 1998 Issued
Array ( [id] => 4122124 [patent_doc_number] => 06052769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction' [patent_app_type] => 1 [patent_app_number] => 9/052881 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9067 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052769.pdf [firstpage_image] =>[orig_patent_app_number] => 052881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052881
Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction Mar 30, 1998 Issued
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