Eliseo Ramos Feliciano

Array ( [id] => 4195120 [patent_doc_number] => 06085303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Seralized race-free virtual barrier network' [patent_app_type] => 1 [patent_app_number] => 8/972010 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6635 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085303.pdf [firstpage_image] =>[orig_patent_app_number] => 972010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3992806 [patent_doc_number] => 05918032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions' [patent_app_type] => 1 [patent_app_number] => 8/959643 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 7404 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918032.pdf [firstpage_image] =>[orig_patent_app_number] => 959643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4049182 [patent_doc_number] => 05943491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Control circuit of mutual exclusion elements' [patent_app_type] => 1 [patent_app_number] => 8/954251 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943491.pdf [firstpage_image] =>[orig_patent_app_number] => 954251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4225972 [patent_doc_number] => 06029242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Data processing system using a shared register bank and a plurality of processors' [patent_app_type] => 1 [patent_app_number] => 8/954541 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9388 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029242.pdf [firstpage_image] =>[orig_patent_app_number] => 954541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3923451 [patent_doc_number] => 05928356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method and apparatus for selectively controlling groups of registers' [patent_app_type] => 1 [patent_app_number] => 8/947541 [patent_app_country] => US [patent_app_date] => 1997-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5456 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928356.pdf [firstpage_image] =>[orig_patent_app_number] => 947541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3951232 [patent_doc_number] => 05940597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method and apparatus for periodically updating entries in a content addressable memory' [patent_app_type] => 1 [patent_app_number] => 8/947081 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7644 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940597.pdf [firstpage_image] =>[orig_patent_app_number] => 947081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3900935 [patent_doc_number] => 05897652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Memory control device and address generating circuit' [patent_app_type] => 1 [patent_app_number] => 8/944719 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 12341 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897652.pdf [firstpage_image] =>[orig_patent_app_number] => 944719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3909997 [patent_doc_number] => 05835734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Electronic processing and control system with programmable hardware' [patent_app_type] => 1 [patent_app_number] => 8/957616 [patent_app_country] => US [patent_app_date] => 1997-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3847 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835734.pdf [firstpage_image] =>[orig_patent_app_number] => 957616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423566 [patent_doc_number] => 06240474 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Pipelined read transfers' [patent_app_type] => 1 [patent_app_number] => 8/931705 [patent_app_country] => US [patent_app_date] => 1997-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6904 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240474.pdf [firstpage_image] =>[orig_patent_app_number] => 931705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057840 [patent_doc_number] => 05913059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Multi-processor system for inheriting contents of register from parent thread to child thread' [patent_app_type] => 1 [patent_app_number] => 8/900643 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 10155 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913059.pdf [firstpage_image] =>[orig_patent_app_number] => 900643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4114634 [patent_doc_number] => 06049861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Locating and sampling of data in parallel processing systems' [patent_app_type] => 1 [patent_app_number] => 8/892402 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6339 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049861.pdf [firstpage_image] =>[orig_patent_app_number] => 892402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3962635 [patent_doc_number] => 05983023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Memory-contained processor' [patent_app_type] => 1 [patent_app_number] => 8/887285 [patent_app_country] => US [patent_app_date] => 1997-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 8264 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983023.pdf [firstpage_image] =>[orig_patent_app_number] => 887285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4026136 [patent_doc_number] => 05941978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method for comparing attribute values of controllable object expressions in a network element' [patent_app_type] => 1 [patent_app_number] => 8/860560 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4345 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941978.pdf [firstpage_image] =>[orig_patent_app_number] => 860560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4068988 [patent_doc_number] => 05970254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Integrated processor and programmable data path chip for reconfigurable computing' [patent_app_type] => 1 [patent_app_number] => 8/884380 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 3462 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970254.pdf [firstpage_image] =>[orig_patent_app_number] => 884380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4023922 [patent_doc_number] => 05890008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Method for dynamically reconfiguring a processor' [patent_app_type] => 1 [patent_app_number] => 8/882171 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8753 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890008.pdf [firstpage_image] =>[orig_patent_app_number] => 882171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4018345 [patent_doc_number] => 05860018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method for tracking pipeline resources in a superscalar processor' [patent_app_type] => 1 [patent_app_number] => 8/881240 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5247 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860018.pdf [firstpage_image] =>[orig_patent_app_number] => 881240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3830719 [patent_doc_number] => 05812856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Efficient ROM and PLA recoding to save chip area' [patent_app_type] => 1 [patent_app_number] => 8/880551 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3248 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812856.pdf [firstpage_image] =>[orig_patent_app_number] => 880551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4211583 [patent_doc_number] => 06044450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Processor for VLIW instruction' [patent_app_type] => 1 [patent_app_number] => 8/824486 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 15471 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044450.pdf [firstpage_image] =>[orig_patent_app_number] => 824486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4260101 [patent_doc_number] => 06092173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system' [patent_app_type] => 1 [patent_app_number] => 8/824871 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 24875 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092173.pdf [firstpage_image] =>[orig_patent_app_number] => 824871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3837504 [patent_doc_number] => 05790898 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Information processing apparatus using finite state machine' [patent_app_type] => 1 [patent_app_number] => 8/828834 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5574 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 500 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790898.pdf [firstpage_image] =>[orig_patent_app_number] => 828834 [rel_patent_id] =>[rel_patent_doc_number] =>)