Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4070228 [patent_doc_number] => 05864692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Method and apparatus for protecting memory-mapped devices from side effects of speculative instructions' [patent_app_type] => 1 [patent_app_number] => 8/767449 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3625 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864692.pdf [firstpage_image] =>[orig_patent_app_number] => 767449 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/767449
Method and apparatus for protecting memory-mapped devices from side effects of speculative instructions Dec 15, 1996 Issued
Array ( [id] => 3894516 [patent_doc_number] => 05799155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Method of data communication and system for carrying out the method' [patent_app_type] => 1 [patent_app_number] => 8/752712 [patent_app_country] => US [patent_app_date] => 1996-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6520 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/799/05799155.pdf [firstpage_image] =>[orig_patent_app_number] => 752712 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/752712
Method of data communication and system for carrying out the method Nov 18, 1996 Issued
Array ( [id] => 3634317 [patent_doc_number] => 05689676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Sequential EEPROM writing apparatus which sequentially and repetitively replaces a head position pointer with a last position pointer' [patent_app_type] => 1 [patent_app_number] => 8/746878 [patent_app_country] => US [patent_app_date] => 1996-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3645 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689676.pdf [firstpage_image] =>[orig_patent_app_number] => 746878 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/746878
Sequential EEPROM writing apparatus which sequentially and repetitively replaces a head position pointer with a last position pointer Nov 17, 1996 Issued
Array ( [id] => 4008935 [patent_doc_number] => 05892981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Memory system and device' [patent_app_type] => 1 [patent_app_number] => 8/729261 [patent_app_country] => US [patent_app_date] => 1996-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4630 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892981.pdf [firstpage_image] =>[orig_patent_app_number] => 729261 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/729261
Memory system and device Oct 9, 1996 Issued
Array ( [id] => 4057844 [patent_doc_number] => 05875347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Neural network processing system using semiconductor memories' [patent_app_type] => 1 [patent_app_number] => 8/723012 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 56 [patent_no_of_words] => 24410 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875347.pdf [firstpage_image] =>[orig_patent_app_number] => 723012 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/723012
Neural network processing system using semiconductor memories Sep 29, 1996 Issued
Array ( [id] => 4057500 [patent_doc_number] => 05875325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Processor having reduced branch history table size through global branch history compression and method of branch prediction utilizing compressed global branch history' [patent_app_type] => 1 [patent_app_number] => 8/716004 [patent_app_country] => US [patent_app_date] => 1996-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3930 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875325.pdf [firstpage_image] =>[orig_patent_app_number] => 716004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/716004
Processor having reduced branch history table size through global branch history compression and method of branch prediction utilizing compressed global branch history Sep 18, 1996 Issued
Array ( [id] => 3787653 [patent_doc_number] => 05774658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Arrangement for accessing media in a network having universal multiple access nodes and carrier sense nodes' [patent_app_type] => 1 [patent_app_number] => 8/713880 [patent_app_country] => US [patent_app_date] => 1996-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5837 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774658.pdf [firstpage_image] =>[orig_patent_app_number] => 713880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713880
Arrangement for accessing media in a network having universal multiple access nodes and carrier sense nodes Sep 16, 1996 Issued
Array ( [id] => 3813130 [patent_doc_number] => 05828858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)' [patent_app_type] => 1 [patent_app_number] => 8/714348 [patent_app_country] => US [patent_app_date] => 1996-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6171 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828858.pdf [firstpage_image] =>[orig_patent_app_number] => 714348 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714348
Worm-hole run-time reconfigurable processor field programmable gate array (FPGA) Sep 15, 1996 Issued
Array ( [id] => 3794748 [patent_doc_number] => 05809309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Processing devices with look-ahead instruction systems and methods' [patent_app_type] => 1 [patent_app_number] => 8/712244 [patent_app_country] => US [patent_app_date] => 1996-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 63 [patent_no_of_words] => 26443 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809309.pdf [firstpage_image] =>[orig_patent_app_number] => 712244 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/712244
Processing devices with look-ahead instruction systems and methods Sep 10, 1996 Issued
Array ( [id] => 3857532 [patent_doc_number] => 05848258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Memory bank addressing scheme' [patent_app_type] => 1 [patent_app_number] => 8/711387 [patent_app_country] => US [patent_app_date] => 1996-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7489 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848258.pdf [firstpage_image] =>[orig_patent_app_number] => 711387 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711387
Memory bank addressing scheme Sep 5, 1996 Issued
Array ( [id] => 3806744 [patent_doc_number] => 05841986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Method for the transmission of binary asynchronous data via a synchronous channel' [patent_app_type] => 1 [patent_app_number] => 8/707601 [patent_app_country] => US [patent_app_date] => 1996-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3466 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841986.pdf [firstpage_image] =>[orig_patent_app_number] => 707601 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/707601
Method for the transmission of binary asynchronous data via a synchronous channel Sep 4, 1996 Issued
Array ( [id] => 3974305 [patent_doc_number] => 05901301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Data processor and method of processing data' [patent_app_type] => 1 [patent_app_number] => 8/699944 [patent_app_country] => US [patent_app_date] => 1996-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 56 [patent_no_of_words] => 17846 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901301.pdf [firstpage_image] =>[orig_patent_app_number] => 699944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/699944
Data processor and method of processing data Aug 19, 1996 Issued
Array ( [id] => 3647868 [patent_doc_number] => 05611075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Bus architecture for digital signal processor allowing time multiplexed access to memory banks' [patent_app_type] => 1 [patent_app_number] => 8/681905 [patent_app_country] => US [patent_app_date] => 1996-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12073 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/611/05611075.pdf [firstpage_image] =>[orig_patent_app_number] => 681905 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/681905
Bus architecture for digital signal processor allowing time multiplexed access to memory banks Jul 28, 1996 Issued
Array ( [id] => 3709289 [patent_doc_number] => 05619720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Digital signal processor having link ports for point-to-point communication' [patent_app_type] => 1 [patent_app_number] => 8/681907 [patent_app_country] => US [patent_app_date] => 1996-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12009 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619720.pdf [firstpage_image] =>[orig_patent_app_number] => 681907 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/681907
Digital signal processor having link ports for point-to-point communication Jul 28, 1996 Issued
Array ( [id] => 3765266 [patent_doc_number] => 05802556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method and apparatus for correcting misaligned instruction data' [patent_app_type] => 1 [patent_app_number] => 8/680808 [patent_app_country] => US [patent_app_date] => 1996-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4023 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802556.pdf [firstpage_image] =>[orig_patent_app_number] => 680808 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/680808
Method and apparatus for correcting misaligned instruction data Jul 15, 1996 Issued
Array ( [id] => 4014997 [patent_doc_number] => 05859789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Arithmetic unit' [patent_app_type] => 1 [patent_app_number] => 8/677837 [patent_app_country] => US [patent_app_date] => 1996-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4543 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859789.pdf [firstpage_image] =>[orig_patent_app_number] => 677837 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/677837
Arithmetic unit Jul 9, 1996 Issued
Array ( [id] => 3788723 [patent_doc_number] => 05774731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage' [patent_app_type] => 1 [patent_app_number] => 8/676053 [patent_app_country] => US [patent_app_date] => 1996-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 23112 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774731.pdf [firstpage_image] =>[orig_patent_app_number] => 676053 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/676053
Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage Jul 4, 1996 Issued
Array ( [id] => 3804091 [patent_doc_number] => 05737629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Dependency checking and forwarding of variable width operands' [patent_app_type] => 1 [patent_app_number] => 8/671439 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 9818 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737629.pdf [firstpage_image] =>[orig_patent_app_number] => 671439 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671439
Dependency checking and forwarding of variable width operands Jun 26, 1996 Issued
Array ( [id] => 4081089 [patent_doc_number] => 05867657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Distributed scheduling in a multiple data server system' [patent_app_type] => 1 [patent_app_number] => 8/684840 [patent_app_country] => US [patent_app_date] => 1996-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6281 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867657.pdf [firstpage_image] =>[orig_patent_app_number] => 684840 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/684840
Distributed scheduling in a multiple data server system Jun 5, 1996 Issued
Array ( [id] => 4015011 [patent_doc_number] => 05859790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Replication of data' [patent_app_type] => 1 [patent_app_number] => 8/649779 [patent_app_country] => US [patent_app_date] => 1996-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 9177 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/859/05859790.pdf [firstpage_image] =>[orig_patent_app_number] => 649779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/649779
Replication of data May 16, 1996 Issued
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