
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3853602
[patent_doc_number] => 05761736
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[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Apparatus and method for implementing multiple scaled states in a state machine'
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[patent_app_number] => 8/648711
[patent_app_country] => US
[patent_app_date] => 1996-05-16
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Array
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[patent_doc_number] => 05852741
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[patent_kind] => NA
[patent_issue_date] => 1998-12-22
[patent_title] => 'VLIW processor which processes compressed instruction format'
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[patent_app_number] => 8/648359
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Array
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[patent_issue_date] => 1998-07-28
[patent_title] => 'Software for producing instructions in a compressed format for a VLIW processor'
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Array
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[patent_issue_date] => 1998-07-07
[patent_title] => 'Enhanced real-time topology analysis system or high speed networks'
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Array
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[patent_title] => 'Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed'
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Array
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[patent_title] => 'Intermediate-grain reconfigurable processing device'
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Array
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[patent_issue_date] => 1998-11-24
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/627801 | Apparatuses and methods for programming parallel computers | Mar 24, 1996 | Issued |
Array
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[id] => 3878541
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Array
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[patent_title] => 'Protection domains in a single address space'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/621759 | Protection domains in a single address space | Mar 21, 1996 | Issued |
Array
(
[id] => 3802222
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Array
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Array
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Array
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Array
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| 08/608965 | INFORMATION PROCESSING APPARATUS USING FINITE STATE MACHINE | Feb 28, 1996 | Abandoned |
Array
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