
Eliseo Ramos Feliciano
Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )
| Most Active Art Unit | 2617 |
| Art Unit(s) | 2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682 |
| Total Applications | 285 |
| Issued Applications | 150 |
| Pending Applications | 66 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3637262
[patent_doc_number] => 05603049
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-11
[patent_title] => 'Bus system servicing plural module requestors with module access identification known to system user'
[patent_app_type] => 1
[patent_app_number] => 8/590378
[patent_app_country] => US
[patent_app_date] => 1996-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/603/05603049.pdf
[firstpage_image] =>[orig_patent_app_number] => 590378
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/590378 | Bus system servicing plural module requestors with module access identification known to system user | Jan 24, 1996 | Issued |
Array
(
[id] => 3681755
[patent_doc_number] => 05600818
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Data protective microprocessor circuit for portable data carriers, for example credit cards'
[patent_app_type] => 1
[patent_app_number] => 8/590872
[patent_app_country] => US
[patent_app_date] => 1996-01-24
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[firstpage_image] =>[orig_patent_app_number] => 590872
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/590872 | Data protective microprocessor circuit for portable data carriers, for example credit cards | Jan 23, 1996 | Issued |
Array
(
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[patent_issue_date] => 1998-10-13
[patent_title] => 'Apparatus and method for aligning variable byte-length instructions to a plurality of issue positions'
[patent_app_type] => 1
[patent_app_number] => 8/582473
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Array
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[patent_doc_number] => 05724527
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[patent_issue_date] => 1998-03-03
[patent_title] => 'Fault-tolerant boot strap mechanism for a multiprocessor system'
[patent_app_type] => 1
[patent_app_number] => 8/579932
[patent_app_country] => US
[patent_app_date] => 1995-12-28
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Array
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[patent_issue_date] => 1998-12-08
[patent_title] => 'Macrocell having a dual purpose input register for use in a logic device'
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[patent_app_number] => 8/578094
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/578094 | Macrocell having a dual purpose input register for use in a logic device | Dec 25, 1995 | Issued |
Array
(
[id] => 4057572
[patent_doc_number] => 05875329
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[patent_issue_date] => 1999-02-23
[patent_title] => 'Intelligent batching of distributed messages'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/577960 | Intelligent batching of distributed messages | Dec 21, 1995 | Issued |
Array
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[patent_title] => 'Method and system for determining network access delay'
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[patent_app_number] => 8/575802
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/575802 | Method and system for determining network access delay | Dec 20, 1995 | Issued |
Array
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[patent_issue_date] => 1998-06-09
[patent_title] => 'Adaptive 128-bit floating point load and store instructions for quad-precision compatibility'
[patent_app_type] => 1
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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