Search

Eliseo Ramos Feliciano

Supervisory Patent Examiner (ID: 8243, Phone: (571)272-7925 , Office: P/2863 )

Most Active Art Unit
2617
Art Unit(s)
2857, 2617, 2681, 2895, 2745, 2817, 2687, 2682
Total Applications
285
Issued Applications
150
Pending Applications
66
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4212223 [patent_doc_number] => 06014514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'System for generating and graphically displaying call stack information for processing elements in a parallel processing system' [patent_app_type] => 1 [patent_app_number] => 8/438437 [patent_app_country] => US [patent_app_date] => 1995-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8953 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014514.pdf [firstpage_image] =>[orig_patent_app_number] => 438437 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/438437
System for generating and graphically displaying call stack information for processing elements in a parallel processing system May 14, 1995 Issued
Array ( [id] => 3919161 [patent_doc_number] => 05752033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Programming device for programmable controller, functional unit for programmable controller, and method of inputting memory display for programming device' [patent_app_type] => 1 [patent_app_number] => 8/439765 [patent_app_country] => US [patent_app_date] => 1995-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 43 [patent_no_of_words] => 15414 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752033.pdf [firstpage_image] =>[orig_patent_app_number] => 439765 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/439765
Programming device for programmable controller, functional unit for programmable controller, and method of inputting memory display for programming device May 11, 1995 Issued
Array ( [id] => 3757381 [patent_doc_number] => 05754742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-19 [patent_title] => 'Setting quantization level to match DCT coefficients' [patent_app_type] => 1 [patent_app_number] => 8/440535 [patent_app_country] => US [patent_app_date] => 1995-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6783 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/754/05754742.pdf [firstpage_image] =>[orig_patent_app_number] => 440535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/440535
Setting quantization level to match DCT coefficients May 11, 1995 Issued
Array ( [id] => 3590711 [patent_doc_number] => 05491829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-13 [patent_title] => 'Method and system for indexing the assignment of intermediate storage buffers in a superscalar processor system' [patent_app_type] => 1 [patent_app_number] => 8/438819 [patent_app_country] => US [patent_app_date] => 1995-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3719 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/491/05491829.pdf [firstpage_image] =>[orig_patent_app_number] => 438819 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/438819
Method and system for indexing the assignment of intermediate storage buffers in a superscalar processor system May 10, 1995 Issued
Array ( [id] => 3678205 [patent_doc_number] => 05669008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Hierarchical fat hypercube architecture for parallel processing systems' [patent_app_type] => 1 [patent_app_number] => 8/435451 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7502 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/669/05669008.pdf [firstpage_image] =>[orig_patent_app_number] => 435451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435451
Hierarchical fat hypercube architecture for parallel processing systems May 4, 1995 Issued
08/429593 NETWORK SWITCH HAVING NETWORK MANAGEMENT AGENT FUNCTIONS DISTRIBUTED AMONG MULTIPLE TRUNK AND SERVICE MODULES Apr 26, 1995 Abandoned
Array ( [id] => 3812237 [patent_doc_number] => 05781787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Parallel program execution time with message consolidation' [patent_app_type] => 1 [patent_app_number] => 8/426805 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 35 [patent_no_of_words] => 9519 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781787.pdf [firstpage_image] =>[orig_patent_app_number] => 426805 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/426805
Parallel program execution time with message consolidation Apr 20, 1995 Issued
Array ( [id] => 3662285 [patent_doc_number] => 05684959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Method for determining topology of a network' [patent_app_type] => 1 [patent_app_number] => 8/425940 [patent_app_country] => US [patent_app_date] => 1995-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 6076 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684959.pdf [firstpage_image] =>[orig_patent_app_number] => 425940 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/425940
Method for determining topology of a network Apr 18, 1995 Issued
Array ( [id] => 3803989 [patent_doc_number] => 05737623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Multi-processor parallel computer architecture using a parallel machine with topology-based mappings of composite grid applications' [patent_app_type] => 1 [patent_app_number] => 8/423483 [patent_app_country] => US [patent_app_date] => 1995-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7816 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737623.pdf [firstpage_image] =>[orig_patent_app_number] => 423483 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/423483
Multi-processor parallel computer architecture using a parallel machine with topology-based mappings of composite grid applications Apr 18, 1995 Issued
Array ( [id] => 3601191 [patent_doc_number] => 05551008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Method and system for resuming data processing in computer' [patent_app_type] => 1 [patent_app_number] => 8/421238 [patent_app_country] => US [patent_app_date] => 1995-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2040 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/551/05551008.pdf [firstpage_image] =>[orig_patent_app_number] => 421238 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/421238
Method and system for resuming data processing in computer Apr 12, 1995 Issued
Array ( [id] => 3626141 [patent_doc_number] => 05535348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Block instruction' [patent_app_type] => 1 [patent_app_number] => 8/420932 [patent_app_country] => US [patent_app_date] => 1995-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 65 [patent_no_of_words] => 26425 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535348.pdf [firstpage_image] =>[orig_patent_app_number] => 420932 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/420932
Block instruction Apr 11, 1995 Issued
Array ( [id] => 3910309 [patent_doc_number] => 05835753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Microprocessor with dynamically extendable pipeline stages and a classifying circuit' [patent_app_type] => 1 [patent_app_number] => 8/421434 [patent_app_country] => US [patent_app_date] => 1995-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5145 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835753.pdf [firstpage_image] =>[orig_patent_app_number] => 421434 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/421434
Microprocessor with dynamically extendable pipeline stages and a classifying circuit Apr 11, 1995 Issued
Array ( [id] => 3742284 [patent_doc_number] => 05671422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Method and apparatus for switching between the modes of a processor' [patent_app_type] => 1 [patent_app_number] => 8/411450 [patent_app_country] => US [patent_app_date] => 1995-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6196 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671422.pdf [firstpage_image] =>[orig_patent_app_number] => 411450 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/411450
Method and apparatus for switching between the modes of a processor Mar 27, 1995 Issued
Array ( [id] => 3877703 [patent_doc_number] => 05796956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'ATM cell switch' [patent_app_type] => 1 [patent_app_number] => 8/406300 [patent_app_country] => US [patent_app_date] => 1995-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5068 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796956.pdf [firstpage_image] =>[orig_patent_app_number] => 406300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/406300
ATM cell switch Mar 16, 1995 Issued
Array ( [id] => 3663006 [patent_doc_number] => 05685008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Computer Processor utilizing logarithmic conversion and method of use thereof' [patent_app_type] => 1 [patent_app_number] => 8/403158 [patent_app_country] => US [patent_app_date] => 1995-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5772 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/685/05685008.pdf [firstpage_image] =>[orig_patent_app_number] => 403158 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/403158
Computer Processor utilizing logarithmic conversion and method of use thereof Mar 12, 1995 Issued
Array ( [id] => 3901309 [patent_doc_number] => 05715440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Branch instruction executing device for tracing branch instruments based on instruction type' [patent_app_type] => 1 [patent_app_number] => 8/400550 [patent_app_country] => US [patent_app_date] => 1995-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8128 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715440.pdf [firstpage_image] =>[orig_patent_app_number] => 400550 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/400550
Branch instruction executing device for tracing branch instruments based on instruction type Mar 7, 1995 Issued
Array ( [id] => 3923354 [patent_doc_number] => 05928349 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Mixed-endian computing environment for a conventional bi-endian computer system' [patent_app_type] => 1 [patent_app_number] => 8/393968 [patent_app_country] => US [patent_app_date] => 1995-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 11634 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928349.pdf [firstpage_image] =>[orig_patent_app_number] => 393968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/393968
Mixed-endian computing environment for a conventional bi-endian computer system Feb 23, 1995 Issued
Array ( [id] => 3567094 [patent_doc_number] => 05574937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Method and apparatus for improving instruction tracing operations in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/380026 [patent_app_country] => US [patent_app_date] => 1995-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5473 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574937.pdf [firstpage_image] =>[orig_patent_app_number] => 380026 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/380026
Method and apparatus for improving instruction tracing operations in a computer system Jan 29, 1995 Issued
08/377685 DOCUMENT PROCESSING APPARATUS FOR DISPLAYING INPUTTED DATA IN A PRINT AREA BASED UPON THE SIZE OF A RECORDING MATERIAL AND THE REPRINTED DATA PRINTED THEREON Jan 24, 1995 Abandoned
Array ( [id] => 3533365 [patent_doc_number] => 05530905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Temporary state preservation for a distributed file service which purges virtual circuit control information after expiration of time limit of inactivity' [patent_app_type] => 1 [patent_app_number] => 8/377670 [patent_app_country] => US [patent_app_date] => 1995-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5164 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530905.pdf [firstpage_image] =>[orig_patent_app_number] => 377670 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/377670
Temporary state preservation for a distributed file service which purges virtual circuit control information after expiration of time limit of inactivity Jan 23, 1995 Issued
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