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Elizabeth Albert

Examiner (ID: 13297, Phone: (571)272-2631 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2913
Total Applications
4788
Issued Applications
4654
Pending Applications
1
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11838800 [patent_doc_number] => 20170220520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'DETERMINING AN OPERATION STATE WITHIN A COMPUTING SYSTEM WITH MULTI-CORE PROCESSING DEVICES' [patent_app_type] => utility [patent_app_number] => 15/010091 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14590 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15010091 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/010091
DETERMINING AN OPERATION STATE WITHIN A COMPUTING SYSTEM WITH MULTI-CORE PROCESSING DEVICES Jan 28, 2016 Abandoned
Array ( [id] => 15284523 [patent_doc_number] => 10514925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-24 [patent_title] => Load speculation recovery [patent_app_type] => utility [patent_app_number] => 15/009614 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12260 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009614 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/009614
Load speculation recovery Jan 27, 2016 Issued
Array ( [id] => 11365979 [patent_doc_number] => 20170003961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'NON-FAULTING COMPUTE INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/941562 [patent_app_country] => US [patent_app_date] => 2015-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10804 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941562 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941562
Non-faulting compute instructions Nov 13, 2015 Issued
Array ( [id] => 11530962 [patent_doc_number] => 20170090940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'EXCEPTION HANDLING FOR APPLICATIONS WITH PREFIX INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/941575 [patent_app_country] => US [patent_app_date] => 2015-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10417 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941575 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941575
Exception handling for applications with prefix instructions Nov 13, 2015 Issued
Array ( [id] => 14798391 [patent_doc_number] => 10402199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor [patent_app_type] => utility [patent_app_number] => 14/920298 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 10385 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920298 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920298
Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor Oct 21, 2015 Issued
Array ( [id] => 15472581 [patent_doc_number] => 10552165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Efficiently managing speculative finish tracking and error handling for load instructions [patent_app_type] => utility [patent_app_number] => 14/887309 [patent_app_country] => US [patent_app_date] => 2015-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 10638 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14887309 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/887309
Efficiently managing speculative finish tracking and error handling for load instructions Oct 18, 2015 Issued
Array ( [id] => 11570521 [patent_doc_number] => 20170109165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'APPARATUS AND METHOD FOR ACCESSING DATA IN A DATA STORE' [patent_app_type] => utility [patent_app_number] => 14/886174 [patent_app_country] => US [patent_app_date] => 2015-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12614 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14886174 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/886174
Apparatus and method for accessing data in a cache in response to an unaligned load instruction Oct 18, 2015 Issued
Array ( [id] => 14149381 [patent_doc_number] => 10255071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Method and apparatus for managing a speculative transaction in a processing unit [patent_app_type] => utility [patent_app_number] => 14/883420 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883420 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/883420
Method and apparatus for managing a speculative transaction in a processing unit Oct 13, 2015 Issued
Array ( [id] => 11530961 [patent_doc_number] => 20170090939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'EXCEPTION HANDLING FOR APPLICATIONS WITH PREFIX INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 14/871970 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10388 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14871970 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/871970
Exception handling for applications with prefix instructions Sep 29, 2015 Issued
Array ( [id] => 14886761 [patent_doc_number] => 10423423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Efficiently managing speculative finish tracking and error handling for load instructions [patent_app_type] => utility [patent_app_number] => 14/869379 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 10738 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869379 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/869379
Efficiently managing speculative finish tracking and error handling for load instructions Sep 28, 2015 Issued
Array ( [id] => 15386843 [patent_doc_number] => 10534606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Run-length encoding decompression [patent_app_type] => utility [patent_app_number] => 14/867929 [patent_app_country] => US [patent_app_date] => 2015-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14587 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14867929 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/867929
Run-length encoding decompression Sep 27, 2015 Issued
Array ( [id] => 10801374 [patent_doc_number] => 20160147531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'DESIGN STRUCTURE FOR MICROPROCESSOR ARITHMETIC LOGIC UNITS' [patent_app_type] => utility [patent_app_number] => 14/865555 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5909 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14865555 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/865555
Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit Sep 24, 2015 Issued
Array ( [id] => 14614903 [patent_doc_number] => 10360153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => System operation queue for transaction [patent_app_type] => utility [patent_app_number] => 14/845343 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15649 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845343 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845343
System operation queue for transaction Sep 3, 2015 Issued
Array ( [id] => 10439188 [patent_doc_number] => 20150324200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'METHODS AND APPARATUS TO COMPILE INSTRUCTIONS FOR A VECTOR OF INSTRUCTION POINTERS PROCESSOR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/803896 [patent_app_country] => US [patent_app_date] => 2015-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14803896 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/803896
Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture to enable speculative execution and avoid data corruption Jul 19, 2015 Issued
Array ( [id] => 15058839 [patent_doc_number] => 10459723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => SIMD instructions for multi-stage cube networks [patent_app_type] => utility [patent_app_number] => 14/804190 [patent_app_country] => US [patent_app_date] => 2015-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7641 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14804190 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/804190
SIMD instructions for multi-stage cube networks Jul 19, 2015 Issued
Array ( [id] => 14395141 [patent_doc_number] => 10310854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Non-faulting compute instructions [patent_app_type] => utility [patent_app_number] => 14/755543 [patent_app_country] => US [patent_app_date] => 2015-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10489 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14755543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/755543
Non-faulting compute instructions Jun 29, 2015 Issued
Array ( [id] => 14427253 [patent_doc_number] => 10318430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => System operation queue for transaction [patent_app_type] => utility [patent_app_number] => 14/751890 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15619 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751890 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751890
System operation queue for transaction Jun 25, 2015 Issued
Array ( [id] => 16185990 [patent_doc_number] => 10719322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Techniques for facilitating cracking and fusion within a same instruction group [patent_app_type] => utility [patent_app_number] => 14/735307 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 19497 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735307 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735307
Techniques for facilitating cracking and fusion within a same instruction group Jun 9, 2015 Issued
Array ( [id] => 10439190 [patent_doc_number] => 20150324202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'DETECTING DATA DEPENDENCIES OF INSTRUCTIONS ASSOCIATED WITH THREADS IN A SIMULTANEOUS MULTITHREADING SCHEME' [patent_app_type] => utility [patent_app_number] => 14/705323 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11286 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705323 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705323
Detecting data dependencies of instructions associated with threads in a simultaneous multithreading scheme May 5, 2015 Issued
Array ( [id] => 10746066 [patent_doc_number] => 20160092217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'Compare Break Instructions' [patent_app_type] => utility [patent_app_number] => 14/704396 [patent_app_country] => US [patent_app_date] => 2015-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14704396 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/704396
Compare Break Instructions May 4, 2015 Abandoned
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