Elizabeth Albert

Array ( [id] => 10746247 [patent_doc_number] => 20160092398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'Conditional Termination and Conditional Termination Predicate Instructions' [patent_app_type] => utility [patent_app_number] => 14/704421 [patent_app_country] => US [patent_app_date] => 2015-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14704421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11131265 [patent_doc_number] => 20160328239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'PERFORMING PARTIAL REGISTER WRITE OPERATIONS IN A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/704108 [patent_app_country] => US [patent_app_date] => 2015-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 20688 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14704108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10493719 [patent_doc_number] => 20150378741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'ARCHITECTURE AND EXECUTION FOR EFFICIENT MIXED PRECISION COMPUTATIONS IN SINGLE INSTRUCTION MULTIPLE DATA/THREAD (SIMD/T) DEVICES' [patent_app_type] => utility [patent_app_number] => 14/672694 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11281 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11086274 [patent_doc_number] => 20160283240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'APPARATUSES AND METHODS TO ACCELERATE VECTOR MULTIPLICATION' [patent_app_type] => utility [patent_app_number] => 14/672156 [patent_app_country] => US [patent_app_date] => 2015-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12589 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11035051 [patent_doc_number] => 20160232006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'FAN OUT OF RESULT OF EXPLICIT DATA GRAPH EXECUTION INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/617910 [patent_app_country] => US [patent_app_date] => 2015-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 18567 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14617910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11027391 [patent_doc_number] => 20160224348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'APPARATUS AND METHOD FOR ARCHITECTURAL PERFORMANCE MONITORING IN BINARY TRANSLATION SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/614264 [patent_app_country] => US [patent_app_date] => 2015-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8964 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14614264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10342366 [patent_doc_number] => 20150227371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'Processors with Support for Compact Branch Instructions & Methods' [patent_app_type] => utility [patent_app_number] => 14/612069 [patent_app_country] => US [patent_app_date] => 2015-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8455 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11027393 [patent_doc_number] => 20160224349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'METHOD AND APPARATUS FOR REALIZING SELF-TIMED PARALLELIZED MANY-CORE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/611140 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7695 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14611140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11020016 [patent_doc_number] => 20160216969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'SYSTEM AND METHOD FOR ADAPTIVELY MANAGING REGISTERS IN AN INSTRUCTION PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/607270 [patent_app_country] => US [patent_app_date] => 2015-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14607270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10982593 [patent_doc_number] => 20160179538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'METHOD AND APPARATUS FOR IMPLEMENTING AND MAINTAINING A STACK OF PREDICATE VALUES WITH STACK SYNCHRONIZATION INSTRUCTIONS IN AN OUT OF ORDER HARDWARE SOFTWARE CO-DESIGNED PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/576915 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18602 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10320605 [patent_doc_number] => 20150205609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'Computer Processor Employing Operand Data With Associated Meta-Data' [patent_app_type] => utility [patent_app_number] => 14/567820 [patent_app_country] => US [patent_app_date] => 2014-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 19694 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14567820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10408777 [patent_doc_number] => 20150293786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'METHOD FOR PROCESSING CR ALGORITHM BY ACTIVELY UTILIZING SHARED MEMORY OF MULTI-PROCESSOR, AND PROCESSOR USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/564508 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2390 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10801373 [patent_doc_number] => 20160147530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'STRUCTURE FOR MICROPROCESSOR ARITHMETIC LOGIC UNITS' [patent_app_type] => utility [patent_app_number] => 14/554194 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5879 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10269025 [patent_doc_number] => 20150154022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'Soft-Partitioning of a Register File Cache' [patent_app_type] => utility [patent_app_number] => 14/548041 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14548041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10471038 [patent_doc_number] => 20150356054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'DATA PROCESSOR AND METHOD FOR DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 14/759205 [patent_app_country] => US [patent_app_date] => 2013-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14759205 [rel_patent_id] =>[rel_patent_doc_number] =>)