Search

Elizabeth Albert

Examiner (ID: 16233, Phone: (571)272-2631 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2913
Total Applications
4788
Issued Applications
4654
Pending Applications
1
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19951061 [patent_doc_number] => 12322431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Refresh address generation circuit and method, memory, and electronic device [patent_app_type] => utility [patent_app_number] => 18/332706 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332706
Refresh address generation circuit and method, memory, and electronic device Jun 8, 2023 Issued
Array ( [id] => 18820777 [patent_doc_number] => 20230395118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => ROW HAMMER MITIGATION [patent_app_type] => utility [patent_app_number] => 18/206241 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206241 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206241
Row hammer mitigation Jun 5, 2023 Issued
Array ( [id] => 19444240 [patent_doc_number] => 12094526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Memory device comprising electrically floating body transistor [patent_app_type] => utility [patent_app_number] => 18/205530 [patent_app_country] => US [patent_app_date] => 2023-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 66 [patent_no_of_words] => 19772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205530
Memory device comprising electrically floating body transistor Jun 2, 2023 Issued
Array ( [id] => 19979991 [patent_doc_number] => 12347477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Integrated circuit memory devices having efficient row hammer management and memory systems including the same [patent_app_type] => utility [patent_app_number] => 18/327335 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 11163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327335
Integrated circuit memory devices having efficient row hammer management and memory systems including the same May 31, 2023 Issued
Array ( [id] => 19979991 [patent_doc_number] => 12347477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Integrated circuit memory devices having efficient row hammer management and memory systems including the same [patent_app_type] => utility [patent_app_number] => 18/327335 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 33 [patent_no_of_words] => 11163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327335 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327335
Integrated circuit memory devices having efficient row hammer management and memory systems including the same May 31, 2023 Issued
Array ( [id] => 19413321 [patent_doc_number] => 12079137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Banked memory architecture for multiple parallel datapath channels in an accelerator [patent_app_type] => utility [patent_app_number] => 18/203527 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11234 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/203527
Banked memory architecture for multiple parallel datapath channels in an accelerator May 29, 2023 Issued
Array ( [id] => 19531506 [patent_doc_number] => 20240355408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => CONTENT ADDRESSABLE MEMORY AND CONTENT ADDRESSABLE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/323430 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323430
Content addressable memory and content addressable memory cell May 24, 2023 Issued
Array ( [id] => 19951058 [patent_doc_number] => 12322428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => SOT-MRAM with shared selector [patent_app_type] => utility [patent_app_number] => 18/321196 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 53 [patent_no_of_words] => 11602 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321196 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321196
SOT-MRAM with shared selector May 21, 2023 Issued
Array ( [id] => 18631493 [patent_doc_number] => 20230290395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => INTEGRATED CIRCUIT WITH ASYMMETRIC ARRANGEMENTS OF MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 18/319969 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319969 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319969
Integrated circuit with asymmetric arrangements of memory arrays May 17, 2023 Issued
Array ( [id] => 19205892 [patent_doc_number] => 20240177791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/320088 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320088
Semiconductor device and method of testing the semiconductor device May 17, 2023 Issued
Array ( [id] => 18789054 [patent_doc_number] => 20230377667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/319584 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319584 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319584
Semiconductor device May 17, 2023 Issued
Array ( [id] => 19475554 [patent_doc_number] => 12105644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Semiconductor device with secure access key and associated methods and systems [patent_app_type] => utility [patent_app_number] => 18/198782 [patent_app_country] => US [patent_app_date] => 2023-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 17751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18198782 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/198782
Semiconductor device with secure access key and associated methods and systems May 16, 2023 Issued
Array ( [id] => 19116119 [patent_doc_number] => 20240127869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => STORAGE DEVICES HAVING MULTI DROP STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/317344 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317344 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/317344
Storage devices having multi drop structure May 14, 2023 Issued
Array ( [id] => 18615541 [patent_doc_number] => 20230282278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => MEMORY CIRCUIT AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/316442 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316442 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/316442
Memory circuit and method of operating the same May 11, 2023 Issued
Array ( [id] => 20345811 [patent_doc_number] => 12469546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Memory array seasoning [patent_app_type] => utility [patent_app_number] => 18/196268 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 9700 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18196268 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/196268
Memory array seasoning May 10, 2023 Issued
Array ( [id] => 20274665 [patent_doc_number] => 12444449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Output block for array of non-volatile memory cells [patent_app_type] => utility [patent_app_number] => 18/195322 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 64 [patent_no_of_words] => 17408 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195322 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195322
Output block for array of non-volatile memory cells May 8, 2023 Issued
Array ( [id] => 19205851 [patent_doc_number] => 20240177750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/144531 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18144531 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/144531
Semiconductor memory device and operation method thereof May 7, 2023 Issued
Array ( [id] => 18743095 [patent_doc_number] => 20230352083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => PSEUDO-STATIC RANDOM-ACCESS MEMORY AND READING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/306249 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306249 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306249
Pseudo-static random-access memory and reading method thereof Apr 24, 2023 Issued
Array ( [id] => 19796082 [patent_doc_number] => 12237047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Method of reading data from self-selecting memory, self-selecting memory performing the same and method of operating self-selecting memory using the same [patent_app_type] => utility [patent_app_number] => 18/303937 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 47 [patent_no_of_words] => 10951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303937
Method of reading data from self-selecting memory, self-selecting memory performing the same and method of operating self-selecting memory using the same Apr 19, 2023 Issued
Array ( [id] => 19964630 [patent_doc_number] => 12334145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Bitcell supporting bit-write-mask function [patent_app_type] => utility [patent_app_number] => 18/301876 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301876
Bitcell supporting bit-write-mask function Apr 16, 2023 Issued
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