Search

Elizabeth Albert

Examiner (ID: 16233, Phone: (571)272-2631 , Office: P/2913 )

Most Active Art Unit
2913
Art Unit(s)
2913
Total Applications
4788
Issued Applications
4654
Pending Applications
1
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18197567 [patent_doc_number] => 20230051086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => Data Writing and Reading Method and Apparatus, and System [patent_app_type] => utility [patent_app_number] => 17/940407 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/940407
Data writing and reading method and apparatus, and system Sep 7, 2022 Issued
Array ( [id] => 19037835 [patent_doc_number] => 20240087650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => SUB-BLOCK STATUS DEPENDENT DEVICE OPERATION [patent_app_type] => utility [patent_app_number] => 17/940498 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940498 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/940498
Sub-block status dependent device operation Sep 7, 2022 Issued
Array ( [id] => 19036259 [patent_doc_number] => 20240086074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => NAND STRING READ VOLTAGE ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/940465 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940465 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/940465
NAND string read voltage adjustment Sep 7, 2022 Issued
Array ( [id] => 18345117 [patent_doc_number] => 20230133227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 17/939273 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939273
Dynamic step voltage level adjustment Sep 6, 2022 Issued
Array ( [id] => 18661053 [patent_doc_number] => 20230307066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/901512 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901512 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901512
Voltage generation circuit and semiconductor memory device Aug 31, 2022 Issued
Array ( [id] => 19670646 [patent_doc_number] => 12183413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Block family error avoidance bin scans after memory device power-on [patent_app_type] => utility [patent_app_number] => 17/898725 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898725
Block family error avoidance bin scans after memory device power-on Aug 29, 2022 Issued
Array ( [id] => 19007366 [patent_doc_number] => 20240071437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => Die Disablement [patent_app_type] => utility [patent_app_number] => 17/823458 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -44 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823458
Die disablement Aug 29, 2022 Issued
Array ( [id] => 18652846 [patent_doc_number] => 20230298686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => REDUNDANCY MANAGING METHOD AND APPARATUS FOR SEMICONDUCTOR MEMORIES [patent_app_type] => utility [patent_app_number] => 17/898126 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898126
Redundancy managing method and apparatus for semiconductor memories Aug 28, 2022 Issued
Array ( [id] => 18240083 [patent_doc_number] => 20230072394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => DATA BUFFER FOR MEMORY DEVICES WITH MEMORY ADDRESS REMAPPING [patent_app_type] => utility [patent_app_number] => 17/897439 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897439
Data buffer for memory devices with memory address remapping Aug 28, 2022 Issued
Array ( [id] => 18639291 [patent_doc_number] => 11763907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Reverse VT-state operation and optimized BiCS device structure [patent_app_type] => utility [patent_app_number] => 17/894028 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 13967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894028 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/894028
Reverse VT-state operation and optimized BiCS device structure Aug 22, 2022 Issued
Array ( [id] => 19720096 [patent_doc_number] => 12205639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Memory device and programming method thereof [patent_app_type] => utility [patent_app_number] => 17/893157 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893157 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893157
Memory device and programming method thereof Aug 21, 2022 Issued
Array ( [id] => 18795586 [patent_doc_number] => 11829366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Apparatuses and methods for on-memory pattern matching [patent_app_type] => utility [patent_app_number] => 17/819793 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819793 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819793
Apparatuses and methods for on-memory pattern matching Aug 14, 2022 Issued
Array ( [id] => 18061447 [patent_doc_number] => 20220392533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => SEQUENTIAL VOLTAGE RAMP-DOWN OF ACCESS LINES OF NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/888041 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10843 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888041 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888041
Sequential voltage ramp-down of access lines of non-volatile memory device Aug 14, 2022 Issued
Array ( [id] => 18061413 [patent_doc_number] => 20220392499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => INTERFACE PROTOCOL CONFIGURATION FOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/888457 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888457 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888457
Interface protocol configuration for memory Aug 14, 2022 Issued
Array ( [id] => 19781277 [patent_doc_number] => 12230315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Model for predicting memory system performance [patent_app_type] => utility [patent_app_number] => 17/819567 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 16847 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819567
Model for predicting memory system performance Aug 11, 2022 Issued
Array ( [id] => 19229381 [patent_doc_number] => 12009022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Semiconductor device for memory device [patent_app_type] => utility [patent_app_number] => 17/885565 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3158 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885565 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885565
Semiconductor device for memory device Aug 10, 2022 Issued
Array ( [id] => 18038869 [patent_doc_number] => 20220383085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY BASED ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/883594 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883594
Method and apparatus for defect-tolerant memory based artificial neural network Aug 7, 2022 Issued
Array ( [id] => 18008202 [patent_doc_number] => 20220366969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => MULTI CHANNEL SEMICONDUCTOR DEVICE HAVING MULTI DIES AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/875865 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875865 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875865
Multi channel semiconductor device having multi dies and operation method thereof Jul 27, 2022 Issued
Array ( [id] => 18795984 [patent_doc_number] => 11829775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Smart compute resistive memory [patent_app_type] => utility [patent_app_number] => 17/876321 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 11334 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876321
Smart compute resistive memory Jul 27, 2022 Issued
Array ( [id] => 18546722 [patent_doc_number] => 11720071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Computing stochastic simulation control parameters [patent_app_type] => utility [patent_app_number] => 17/815541 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815541
Computing stochastic simulation control parameters Jul 26, 2022 Issued
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