Elizabeth Houston

Array ( [id] => 20283840 [patent_doc_number] => 20250309082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Through Package Vertical Interconnect and Method of Making Same [patent_app_type] => utility [patent_app_number] => 19/238914 [patent_app_country] => US [patent_app_date] => 2025-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19238914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20146770 [patent_doc_number] => 12381117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon [patent_app_type] => utility [patent_app_number] => 18/792267 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18792267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19546503 [patent_doc_number] => 20240363539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SEMICONDUCTOR DEVICE HAVING CONTACT PLUG CONNECTED TO GATE STRUCTURE ON PMOS REGION [patent_app_type] => utility [patent_app_number] => 18/764355 [patent_app_country] => US [patent_app_date] => 2024-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19532041 [patent_doc_number] => 20240355943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => ELECTRONIC IMAGING DETECTOR WITH THERMAL CONDUCTION LAYER [patent_app_type] => utility [patent_app_number] => 18/761587 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19515860 [patent_doc_number] => 20240347546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING SEGMENTED INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/755041 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19420941 [patent_doc_number] => 20240297065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => CURVED SEMICONDUCTOR DIE SYSTEMS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/661094 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19421111 [patent_doc_number] => 20240297235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => AIR SPACERS AROUND CONTACT PLUGS AND METHOD FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/658521 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19420670 [patent_doc_number] => 20240296794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => ORGANIC LIGHT-EMITTING DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/658590 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19420975 [patent_doc_number] => 20240297099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SELF-ALIGNED CONTACT OPENINGS FOR BACKSIDE THROUGH SUBSTRATE VIAS [patent_app_type] => utility [patent_app_number] => 18/648132 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19888343 [patent_doc_number] => 12274092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Resistance measuring structures of stacked devices [patent_app_type] => utility [patent_app_number] => 18/406345 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20457511 [patent_doc_number] => 12520583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Stacking nanosheet transistors with an intermediate gate structure absent [patent_app_type] => utility [patent_app_number] => 18/404815 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 39 [patent_no_of_words] => 4298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20111585 [patent_doc_number] => 12362321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 18/398194 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 41 [patent_no_of_words] => 8567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18398194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19335612 [patent_doc_number] => 20240250042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE ASSEMBLIES WITH DIRECT LEADFRAME ATTACHMENT [patent_app_type] => utility [patent_app_number] => 18/390928 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19038330 [patent_doc_number] => 20240088145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => INTEGRATED CIRCUITS WITH GATE CUT FEATURES [patent_app_type] => utility [patent_app_number] => 18/519263 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20418336 [patent_doc_number] => 12501640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/518190 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 3971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19038288 [patent_doc_number] => 20240088103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => 3D TRENCH CAPACITOR FOR INTEGRATED PASSIVE DEVICES [patent_app_type] => utility [patent_app_number] => 18/512092 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18512092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19741272 [patent_doc_number] => 12218118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Electronic device [patent_app_type] => utility [patent_app_number] => 18/508255 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6312 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19023186 [patent_doc_number] => 20240079357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => POST PASSIVATION INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/507817 [patent_app_country] => US [patent_app_date] => 2023-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18507817 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19007873 [patent_doc_number] => 20240071944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CHIP FABRICATION METHOD AND PRODUCT [patent_app_type] => utility [patent_app_number] => 18/503673 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18991154 [patent_doc_number] => 20240063123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => THROUGH SILICON BURIED POWER RAIL IMPLEMENTED BACKSIDE POWER DISTRIBUTION NETWORK SEMICONDUCTOR ARCHITECTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/386497 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386497 [rel_patent_id] =>[rel_patent_doc_number] =>)