Elizabeth Houston

Array ( [id] => 7647029 [patent_doc_number] => 06476489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Apparatus and manufacturing method for semiconductor device adopting NA interlayer contact structure' [patent_app_type] => B1 [patent_app_number] => 09/258292 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2913 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476489.pdf [firstpage_image] =>[orig_patent_app_number] => 09258292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7647029 [patent_doc_number] => 06476489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Apparatus and manufacturing method for semiconductor device adopting NA interlayer contact structure' [patent_app_type] => B1 [patent_app_number] => 09/258292 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2913 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476489.pdf [firstpage_image] =>[orig_patent_app_number] => 09258292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7647029 [patent_doc_number] => 06476489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Apparatus and manufacturing method for semiconductor device adopting NA interlayer contact structure' [patent_app_type] => B1 [patent_app_number] => 09/258292 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2913 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476489.pdf [firstpage_image] =>[orig_patent_app_number] => 09258292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7647029 [patent_doc_number] => 06476489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Apparatus and manufacturing method for semiconductor device adopting NA interlayer contact structure' [patent_app_type] => B1 [patent_app_number] => 09/258292 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2913 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476489.pdf [firstpage_image] =>[orig_patent_app_number] => 09258292 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4253704 [patent_doc_number] => 06137179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and TI/TIN bit lines' [patent_app_type] => 1 [patent_app_number] => 9/257832 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4372 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137179.pdf [firstpage_image] =>[orig_patent_app_number] => 257832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4253633 [patent_doc_number] => 06137175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Semiconductor device with multi-layer wiring' [patent_app_type] => 1 [patent_app_number] => 9/253362 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 48 [patent_no_of_words] => 10483 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137175.pdf [firstpage_image] =>[orig_patent_app_number] => 253362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4253239 [patent_doc_number] => 06137147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Bipolar transistor and semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/253503 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2324 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137147.pdf [firstpage_image] =>[orig_patent_app_number] => 253503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4111576 [patent_doc_number] => 06023100 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects' [patent_app_type] => 1 [patent_app_number] => 9/248723 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2576 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023100.pdf [firstpage_image] =>[orig_patent_app_number] => 248723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7963783 [patent_doc_number] => 06680537 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Semiconductor device having a dual damascene interconnect structure and method for manufacturing same' [patent_app_type] => B1 [patent_app_number] => 09/241461 [patent_app_country] => US [patent_app_date] => 1999-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 2185 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680537.pdf [firstpage_image] =>[orig_patent_app_number] => 09241461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4388053 [patent_doc_number] => 06278157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements' [patent_app_type] => 1 [patent_app_number] => 9/240991 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3725 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278157.pdf [firstpage_image] =>[orig_patent_app_number] => 240991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4253214 [patent_doc_number] => 06137145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon' [patent_app_type] => 1 [patent_app_number] => 9/237773 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4861 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137145.pdf [firstpage_image] =>[orig_patent_app_number] => 237773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4355144 [patent_doc_number] => 06215147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Flash memory structure' [patent_app_type] => 1 [patent_app_number] => 9/235261 [patent_app_country] => US [patent_app_date] => 1999-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2175 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215147.pdf [firstpage_image] =>[orig_patent_app_number] => 235261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4243730 [patent_doc_number] => 06091097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Semiconductor device and a method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/233963 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 20 [patent_no_of_words] => 4591 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091097.pdf [firstpage_image] =>[orig_patent_app_number] => 233963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7625137 [patent_doc_number] => 06724033 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Fork-like memory structure for ULSI DRAM' [patent_app_type] => B1 [patent_app_number] => 09/233820 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2792 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724033.pdf [firstpage_image] =>[orig_patent_app_number] => 09233820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4362990 [patent_doc_number] => 06175160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Flip-chip having an on-chip cache memory' [patent_app_type] => 1 [patent_app_number] => 9/227983 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175160.pdf [firstpage_image] =>[orig_patent_app_number] => 227983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4113371 [patent_doc_number] => 06057583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Transistor with low resistance metal source and drain vertically displaced from the channel' [patent_app_type] => 1 [patent_app_number] => 9/227511 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 6487 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057583.pdf [firstpage_image] =>[orig_patent_app_number] => 227511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373085 [patent_doc_number] => 06274900 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Semiconductor device architectures including UV transmissive nitride layers' [patent_app_type] => 1 [patent_app_number] => 9/225581 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3479 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274900.pdf [firstpage_image] =>[orig_patent_app_number] => 225581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4401261 [patent_doc_number] => 06297530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Self aligned channel implantation' [patent_app_type] => 1 [patent_app_number] => 9/418181 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3693 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297530.pdf [firstpage_image] =>[orig_patent_app_number] => 418181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4113485 [patent_doc_number] => 06057590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Structure of polysilicon load for static random access memory' [patent_app_type] => 1 [patent_app_number] => 9/217611 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1850 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057590.pdf [firstpage_image] =>[orig_patent_app_number] => 217611 [rel_patent_id] =>[rel_patent_doc_number] =>)