Elizabeth Houston

Array ( [id] => 1476334 [patent_doc_number] => 06388299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Sensor assembly and method' [patent_app_type] => B1 [patent_app_number] => 09/208781 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6641 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388299.pdf [firstpage_image] =>[orig_patent_app_number] => 09208781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1476330 [patent_doc_number] => 06388298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Detached drain MOSFET' [patent_app_type] => B1 [patent_app_number] => 09/207651 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 16037 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388298.pdf [firstpage_image] =>[orig_patent_app_number] => 09207651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4301178 [patent_doc_number] => 06198131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'High-voltage metal-oxide semiconductor' [patent_app_type] => 1 [patent_app_number] => 9/206451 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198131.pdf [firstpage_image] =>[orig_patent_app_number] => 206451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1351997 [patent_doc_number] => 06583464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Memory cell using amorphous material to stabilize the boundary face between polycrystalline semiconductor material of a capacitor and monocrystalline semiconductor material of a transistor' [patent_app_type] => B1 [patent_app_number] => 09/201733 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3669 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583464.pdf [firstpage_image] =>[orig_patent_app_number] => 09201733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4282400 [patent_doc_number] => 06281545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Multi-level, split-gate, flash memory cell' [patent_app_type] => 1 [patent_app_number] => 9/199130 [patent_app_country] => US [patent_app_date] => 1998-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3188 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281545.pdf [firstpage_image] =>[orig_patent_app_number] => 199130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4113306 [patent_doc_number] => 06057578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Protective integrated structure with biasing devices having a predetermined reverse conduction threshold' [patent_app_type] => 1 [patent_app_number] => 9/195912 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3518 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057578.pdf [firstpage_image] =>[orig_patent_app_number] => 195912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4412722 [patent_doc_number] => 06239458 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Polysilicon-via structure for four transistor, triple polysilicon layer SRAM cell including two polysilicon layer load resistor' [patent_app_type] => 1 [patent_app_number] => 9/193972 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6574 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239458.pdf [firstpage_image] =>[orig_patent_app_number] => 193972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1144770 [patent_doc_number] => 06777772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Semiconductor device having improved trench structure' [patent_app_type] => B1 [patent_app_number] => 09/189870 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3243 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777772.pdf [firstpage_image] =>[orig_patent_app_number] => 09189870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4282545 [patent_doc_number] => 06281555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Integrated circuit having isolation structures' [patent_app_type] => 1 [patent_app_number] => 9/187861 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2754 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281555.pdf [firstpage_image] =>[orig_patent_app_number] => 187861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4297606 [patent_doc_number] => 06236101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Metallization outside protective overcoat for improved capacitors and inductors' [patent_app_type] => 1 [patent_app_number] => 9/183821 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 66 [patent_no_of_words] => 4216 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236101.pdf [firstpage_image] =>[orig_patent_app_number] => 183821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4360854 [patent_doc_number] => 06218720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Semiconductor topography employing a nitrogenated shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/176131 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 5084 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218720.pdf [firstpage_image] =>[orig_patent_app_number] => 176131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4243620 [patent_doc_number] => 06091089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/175537 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3421 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091089.pdf [firstpage_image] =>[orig_patent_app_number] => 175537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4095092 [patent_doc_number] => 06133633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method for building interconnect structures by injection molded solder and structures built' [patent_app_type] => 1 [patent_app_number] => 9/169249 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4819 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133633.pdf [firstpage_image] =>[orig_patent_app_number] => 169249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324535 [patent_doc_number] => 06249014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Hydrogen barrier encapsulation techniques for the control of hydrogen induced degradation of ferroelectric capacitors in conjunction with multilevel metal processing for non-volatile integrated circuit memory devices' [patent_app_type] => 1 [patent_app_number] => 9/164952 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7040 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249014.pdf [firstpage_image] =>[orig_patent_app_number] => 164952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422581 [patent_doc_number] => 06194764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Integrated semiconductor circuit with protection structure for protecting against electrostatic discharge' [patent_app_type] => 1 [patent_app_number] => 9/163881 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194764.pdf [firstpage_image] =>[orig_patent_app_number] => 163881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4333576 [patent_doc_number] => 06320232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Integrated semiconductor circuit with protective structure for protection against electrostatic discharge' [patent_app_type] => 1 [patent_app_number] => 9/164121 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5178 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320232.pdf [firstpage_image] =>[orig_patent_app_number] => 164121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4123817 [patent_doc_number] => 06072237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Borderless contact structure' [patent_app_type] => 1 [patent_app_number] => 9/163382 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3053 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 562 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072237.pdf [firstpage_image] =>[orig_patent_app_number] => 163382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4176711 [patent_doc_number] => 06140688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Semiconductor device with self-aligned metal-containing gate' [patent_app_type] => 1 [patent_app_number] => 9/157627 [patent_app_country] => US [patent_app_date] => 1998-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 7155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140688.pdf [firstpage_image] =>[orig_patent_app_number] => 157627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7645288 [patent_doc_number] => 06472684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Nonvolatile memory and manufacturing method thereof' [patent_app_type] => B1 [patent_app_number] => 09/156913 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 57 [patent_no_of_words] => 12622 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472684.pdf [firstpage_image] =>[orig_patent_app_number] => 09156913 [rel_patent_id] =>[rel_patent_doc_number] =>)