Search

Elizabeth Houston

Supervisory Patent Examiner (ID: 14219, Phone: (571)272-7134 , Office: P/3731 )

Most Active Art Unit
3731
Art Unit(s)
3773, 3731, 3771, 3753
Total Applications
616
Issued Applications
244
Pending Applications
23
Abandoned Applications
359

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18555306 [patent_doc_number] => 20230253323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => LAYOUT OF CONDUCTIVE VIAS FOR SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/665367 [patent_app_country] => US [patent_app_date] => 2022-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8551 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665367 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/665367
Layout of conductive vias for semiconductor device Feb 3, 2022 Issued
Array ( [id] => 17917563 [patent_doc_number] => 20220319959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SEMICONDUCTOR STRUCTURE, METHOD FOR FORMING SAME AND STACKED STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/648903 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648903
Semiconductor structure, method for forming same and stacked structure Jan 24, 2022 Issued
Array ( [id] => 18507625 [patent_doc_number] => 11705454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Active regions via contacts having various shaped segments off-set from gate via contact [patent_app_type] => utility [patent_app_number] => 17/582357 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 6722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582357
Active regions via contacts having various shaped segments off-set from gate via contact Jan 23, 2022 Issued
Array ( [id] => 19610951 [patent_doc_number] => 12159832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Integrated circuit device [patent_app_type] => utility [patent_app_number] => 17/648598 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 13604 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648598
Integrated circuit device Jan 20, 2022 Issued
Array ( [id] => 19828765 [patent_doc_number] => 12249557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Semiconductor device including backside wiring structure with super via [patent_app_type] => utility [patent_app_number] => 17/581084 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581084
Semiconductor device including backside wiring structure with super via Jan 20, 2022 Issued
Array ( [id] => 18514655 [patent_doc_number] => 20230230916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/577800 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577800 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577800
Gate to source drain interconnects Jan 17, 2022 Issued
Array ( [id] => 18975234 [patent_doc_number] => 20240055326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/260669 [patent_app_country] => US [patent_app_date] => 2022-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18260669 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/260669
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Jan 16, 2022 Pending
Array ( [id] => 19781533 [patent_doc_number] => 12230571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Integrated circuit devices including a power rail and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/576007 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5607 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/576007
Integrated circuit devices including a power rail and methods of forming the same Jan 13, 2022 Issued
Array ( [id] => 19783271 [patent_doc_number] => 12232326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Memory device and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/571564 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 12285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571564
Memory device and method of forming the same Jan 9, 2022 Issued
Array ( [id] => 19781515 [patent_doc_number] => 12230553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Semiconductor structure, manufacturing method of semiconductor structure and stacked structure [patent_app_type] => utility [patent_app_number] => 17/647458 [patent_app_country] => US [patent_app_date] => 2022-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4211 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647458
Semiconductor structure, manufacturing method of semiconductor structure and stacked structure Jan 7, 2022 Issued
Array ( [id] => 18061802 [patent_doc_number] => 20220392889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => CAPACITOR STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/647046 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647046
Semiconductor device and method for forming capacitor structure Jan 4, 2022 Issued
Array ( [id] => 18230300 [patent_doc_number] => 20230069294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MULTI-DIE COMMUNICATIONS COUPLINGS USING A SINGLE BRIDGE DIE [patent_app_type] => utility [patent_app_number] => 17/563921 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563921 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563921
MULTI-DIE COMMUNICATIONS COUPLINGS USING A SINGLE BRIDGE DIE Dec 27, 2021 Pending
Array ( [id] => 18704774 [patent_doc_number] => 11791291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Multiplexer cell and semiconductor device having camouflage design, and method for forming multiplexer cell [patent_app_type] => utility [patent_app_number] => 17/559568 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 14324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559568 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559568
Multiplexer cell and semiconductor device having camouflage design, and method for forming multiplexer cell Dec 21, 2021 Issued
Array ( [id] => 18874789 [patent_doc_number] => 11862612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => 3D trench capacitor for integrated passive devices [patent_app_type] => utility [patent_app_number] => 17/555969 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 40 [patent_no_of_words] => 14447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555969 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555969
3D trench capacitor for integrated passive devices Dec 19, 2021 Issued
Array ( [id] => 17692454 [patent_doc_number] => 20220199747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/551754 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551754
Display apparatus Dec 14, 2021 Issued
Array ( [id] => 18279949 [patent_doc_number] => 20230095421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING A METAL RESISTOR AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/547700 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547700
Integrated circuit devices including a metal resistor and methods of forming the same Dec 9, 2021 Issued
Array ( [id] => 18081299 [patent_doc_number] => 20220406911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => ELECTRONIC DEVICE INCLUDING TWO-DIMENSIONAL MATERIAL AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/545373 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545373
Electronic device including two-dimensional material and method of fabricating the same Dec 7, 2021 Issued
Array ( [id] => 18423969 [patent_doc_number] => 20230178433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => BURIED POWER RAIL AT TIGHT CELL-TO-CELL SPACE [patent_app_type] => utility [patent_app_number] => 17/545073 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545073 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545073
Buried power rail at tight cell-to-cell space Dec 7, 2021 Issued
Array ( [id] => 20532167 [patent_doc_number] => 12550620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Top electrode to metal line connection for magneto-resistive random-access memory stack height reduction [patent_app_type] => utility [patent_app_number] => 17/457565 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 1029 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457565 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457565
TOP ELECTRODE TO METAL LINE CONNECTION FOR MAGNETO-RESISTIVE RANDOM-ACCESS MEMORY STACK HEIGHT REDUCTION Dec 2, 2021 Issued
Array ( [id] => 19781514 [patent_doc_number] => 12230552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Recess structure for padless stack via [patent_app_type] => utility [patent_app_number] => 17/455576 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 13560 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455576 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455576
Recess structure for padless stack via Nov 17, 2021 Issued
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