Search

Elizabeth Houston

Supervisory Patent Examiner (ID: 14219, Phone: (571)272-7134 , Office: P/3731 )

Most Active Art Unit
3731
Art Unit(s)
3773, 3731, 3771, 3753
Total Applications
616
Issued Applications
244
Pending Applications
23
Abandoned Applications
359

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17442198 [patent_doc_number] => 20220062703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => INFORMATION PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/454578 [patent_app_country] => US [patent_app_date] => 2021-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454578 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454578
Information processing system Nov 10, 2021 Issued
Array ( [id] => 19414821 [patent_doc_number] => 12080658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Integrated circuit device with antenna effect protection circuit and method of manufacturing [patent_app_type] => utility [patent_app_number] => 17/522376 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522376 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522376
Integrated circuit device with antenna effect protection circuit and method of manufacturing Nov 8, 2021 Issued
Array ( [id] => 17431754 [patent_doc_number] => 20220059463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH POROUS INSULATING LAYERS [patent_app_type] => utility [patent_app_number] => 17/520981 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520981 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520981
Method for fabricating semiconductor device with porous insulating layers Nov 7, 2021 Issued
Array ( [id] => 19679381 [patent_doc_number] => 12191254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Electronic devices including tiered stacks including conductive structures isolated by slot structures, and related systems and methods [patent_app_type] => utility [patent_app_number] => 17/453041 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 18859 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453041 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453041
Electronic devices including tiered stacks including conductive structures isolated by slot structures, and related systems and methods Oct 31, 2021 Issued
Array ( [id] => 18767021 [patent_doc_number] => 11817433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Light-emitting device [patent_app_type] => utility [patent_app_number] => 17/515349 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 12881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515349 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/515349
Light-emitting device Oct 28, 2021 Issued
Array ( [id] => 19183825 [patent_doc_number] => 11990426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/451393 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5089 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451393
Semiconductor structure Oct 18, 2021 Issued
Array ( [id] => 19446309 [patent_doc_number] => 12096622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Directional etch for improved dual deck three-dimensional NAND architecture margin [patent_app_type] => utility [patent_app_number] => 17/502140 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 4634 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502140
Directional etch for improved dual deck three-dimensional NAND architecture margin Oct 14, 2021 Issued
Array ( [id] => 20230492 [patent_doc_number] => 12419157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Double gate thin film transistor device with mixed semiconductor layers [patent_app_type] => utility [patent_app_number] => 17/450504 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5790 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450504
Double gate thin film transistor device with mixed semiconductor layers Oct 10, 2021 Issued
Array ( [id] => 18696573 [patent_doc_number] => 20230327014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => TRENCH SiC POWER SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/026790 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5294 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18026790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/026790
TRENCH SiC POWER SEMICONDUCTOR DEVICE Oct 7, 2021 Pending
Array ( [id] => 17486222 [patent_doc_number] => 20220093726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => THREE-DIMENSIONAL CAPACITIVE STRUCTURES AND THEIR MANUFACTURING METHODS [patent_app_type] => utility [patent_app_number] => 17/496185 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496185
Three-dimensional capacitive structures and their manufacturing methods Oct 6, 2021 Issued
Array ( [id] => 17373735 [patent_doc_number] => 20220028787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SEMICONDUCTOR DEVICE HAVING CONTACT PLUG CONNECTED TO GATE STRUCTURE ON PMOS REGION [patent_app_type] => utility [patent_app_number] => 17/493852 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493852
Semiconductor device having contact plug connected to gate structure on PMOS region Oct 4, 2021 Issued
Array ( [id] => 17855552 [patent_doc_number] => 20220285595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/449414 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17449414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/449414
Display apparatus Sep 28, 2021 Issued
Array ( [id] => 17486002 [patent_doc_number] => 20220093506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/448892 [patent_app_country] => US [patent_app_date] => 2021-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448892
Semiconductor structure with conductive plug and capacitor array Sep 25, 2021 Issued
Array ( [id] => 17917694 [patent_doc_number] => 20220320090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => NANOSHEET DEVICE ARCHITECTURE FOR CELL-HEIGHT SCALING [patent_app_type] => utility [patent_app_number] => 17/476140 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476140 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476140
Nanosheet device architecture for cell-height scaling Sep 14, 2021 Issued
Array ( [id] => 18228958 [patent_doc_number] => 20230067952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE SEGMENTED INTERCONNECT [patent_app_type] => utility [patent_app_number] => 17/463022 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463022
Semiconductor device segmented interconnect Aug 30, 2021 Issued
Array ( [id] => 17566533 [patent_doc_number] => 20220130682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => STIFFENER PACKAGE AND METHOD OF FABRICATING STIFFENER PACKAGE [patent_app_type] => utility [patent_app_number] => 17/459706 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459706 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459706
Stiffener package and method of fabricating stiffener package Aug 26, 2021 Issued
Array ( [id] => 17277897 [patent_doc_number] => 20210384095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => FAN-OUT SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/409281 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409281
Fan-out semiconductor package Aug 22, 2021 Issued
Array ( [id] => 18113149 [patent_doc_number] => 20230006029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => Semiconductor Device Including Three-Dimensional Inductor Structure and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 17/408485 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408485
Semiconductor device including three-dimensional inductor structure and method of forming the same Aug 22, 2021 Issued
Array ( [id] => 17431668 [patent_doc_number] => 20220059377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => INSPECTION DEVICE, RESIN MOLDING APPARATUS, AND METHOD OF MANUFACTURING RESIN MOLDED PRODUCT [patent_app_type] => utility [patent_app_number] => 17/402416 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402416 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402416
INSPECTION DEVICE, RESIN MOLDING APPARATUS, AND METHOD OF MANUFACTURING RESIN MOLDED PRODUCT Aug 12, 2021 Abandoned
Array ( [id] => 17263130 [patent_doc_number] => 20210376115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/397646 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397646
Semiconductor device and manufacturing method thereof Aug 8, 2021 Issued
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