
Elizabeth Mary Cole Imani
Examiner (ID: 2226, Phone: (571)272-1475 , Office: P/1789 )
| Most Active Art Unit | 1789 |
| Art Unit(s) | 1771, 1314, 1794, 1789, 1798, 1504, 1782 |
| Total Applications | 1863 |
| Issued Applications | 671 |
| Pending Applications | 224 |
| Abandoned Applications | 1000 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4874664
[patent_doc_number] => 20080201398
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-21
[patent_title] => 'Determination of a Modular Inverse'
[patent_app_type] => utility
[patent_app_number] => 11/915081
[patent_app_country] => US
[patent_app_date] => 2006-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2556
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0201/20080201398.pdf
[firstpage_image] =>[orig_patent_app_number] => 11915081
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/915081 | Determination of a Modular Inverse | May 18, 2006 | Abandoned |
Array
(
[id] => 7690272
[patent_doc_number] => 20070233761
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'Crossbar arithmetic processor'
[patent_app_type] => utility
[patent_app_number] => 11/395232
[patent_app_country] => US
[patent_app_date] => 2006-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 8995
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0233/20070233761.pdf
[firstpage_image] =>[orig_patent_app_number] => 11395232
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/395232 | Crossbar arithmetic processor | Apr 2, 2006 | Abandoned |
Array
(
[id] => 4730014
[patent_doc_number] => 20080208941
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-08-28
[patent_title] => 'Interpolation Process Circuit'
[patent_app_type] => utility
[patent_app_number] => 11/915085
[patent_app_country] => US
[patent_app_date] => 2006-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8216
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0208/20080208941.pdf
[firstpage_image] =>[orig_patent_app_number] => 11915085
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/915085 | Interpolation Process Circuit | Feb 7, 2006 | Abandoned |
Array
(
[id] => 5161781
[patent_doc_number] => 20070174825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-26
[patent_title] => 'Apparatus and method for optimizing scalar code executed on a SIMD engine by alignment of SIMD slots'
[patent_app_type] => utility
[patent_app_number] => 11/339591
[patent_app_country] => US
[patent_app_date] => 2006-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6359
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20070174825.pdf
[firstpage_image] =>[orig_patent_app_number] => 11339591
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/339591 | Apparatus and method for optimizing scalar code executed on a SIMD engine by alignment of SIMD slots | Jan 24, 2006 | Abandoned |
Array
(
[id] => 5651188
[patent_doc_number] => 20060136923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'System for distributed task execution'
[patent_app_type] => utility
[patent_app_number] => 11/317721
[patent_app_country] => US
[patent_app_date] => 2005-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 15802
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0136/20060136923.pdf
[firstpage_image] =>[orig_patent_app_number] => 11317721
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/317721 | System for distributed task execution | Dec 21, 2005 | Abandoned |
Array
(
[id] => 5184609
[patent_doc_number] => 20070055963
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-08
[patent_title] => 'Compile target and compiler flag extraction in program analysis and transformation systems'
[patent_app_type] => utility
[patent_app_number] => 11/222099
[patent_app_country] => US
[patent_app_date] => 2005-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3347
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0055/20070055963.pdf
[firstpage_image] =>[orig_patent_app_number] => 11222099
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/222099 | Compile target and compiler flag extraction in program analysis and transformation systems | Sep 7, 2005 | Abandoned |
Array
(
[id] => 7256301
[patent_doc_number] => 20050273765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-08
[patent_title] => 'Object-oriented creation breakpoints'
[patent_app_type] => utility
[patent_app_number] => 11/197895
[patent_app_country] => US
[patent_app_date] => 2005-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6497
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20050273765.pdf
[firstpage_image] =>[orig_patent_app_number] => 11197895
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/197895 | Object-oriented creation breakpoints | Aug 4, 2005 | Abandoned |
Array
(
[id] => 5644377
[patent_doc_number] => 20060282832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-14
[patent_title] => 'Calculating module runtimes on multiple platforms'
[patent_app_type] => utility
[patent_app_number] => 11/149997
[patent_app_country] => US
[patent_app_date] => 2005-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4439
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0282/20060282832.pdf
[firstpage_image] =>[orig_patent_app_number] => 11149997
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/149997 | Calculating module runtimes on multiple platforms | Jun 9, 2005 | Abandoned |
Array
(
[id] => 6953762
[patent_doc_number] => 20050228857
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Method for a group of services to operate in two modes simultaneously'
[patent_app_type] => utility
[patent_app_number] => 11/147727
[patent_app_country] => US
[patent_app_date] => 2005-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 11626
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0228/20050228857.pdf
[firstpage_image] =>[orig_patent_app_number] => 11147727
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/147727 | Method for a group of services to operate in two modes simultaneously | Jun 7, 2005 | Abandoned |
Array
(
[id] => 7192419
[patent_doc_number] => 20050193051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'Logic circuit'
[patent_app_type] => utility
[patent_app_number] => 11/115149
[patent_app_country] => US
[patent_app_date] => 2005-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 33426
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20050193051.pdf
[firstpage_image] =>[orig_patent_app_number] => 11115149
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/115149 | Logic circuit | Apr 26, 2005 | Abandoned |
Array
(
[id] => 6944006
[patent_doc_number] => 20050196055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-08
[patent_title] => 'Method and system for codifying signals that ensure high fidelity reconstruction'
[patent_app_type] => utility
[patent_app_number] => 11/073306
[patent_app_country] => US
[patent_app_date] => 2005-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7378
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0196/20050196055.pdf
[firstpage_image] =>[orig_patent_app_number] => 11073306
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/073306 | Method and system for codifying signals that ensure high fidelity reconstruction | Mar 2, 2005 | Abandoned |
Array
(
[id] => 856530
[patent_doc_number] => 07380249
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-27
[patent_title] => 'Object manager for common information model'
[patent_app_type] => utility
[patent_app_number] => 11/070011
[patent_app_country] => US
[patent_app_date] => 2005-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8456
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/380/07380249.pdf
[firstpage_image] =>[orig_patent_app_number] => 11070011
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/070011 | Object manager for common information model | Feb 28, 2005 | Issued |
Array
(
[id] => 778159
[patent_doc_number] => 07003779
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-21
[patent_title] => 'Hierarchical connected graph model for implementation of event management design'
[patent_app_type] => utility
[patent_app_number] => 11/059894
[patent_app_country] => US
[patent_app_date] => 2005-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 7214
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/003/07003779.pdf
[firstpage_image] =>[orig_patent_app_number] => 11059894
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/059894 | Hierarchical connected graph model for implementation of event management design | Feb 16, 2005 | Issued |
Array
(
[id] => 5728460
[patent_doc_number] => 20060059221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-16
[patent_title] => 'Multiply instructions for modular exponentiation'
[patent_app_type] => utility
[patent_app_number] => 11/044648
[patent_app_country] => US
[patent_app_date] => 2005-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7851
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0059/20060059221.pdf
[firstpage_image] =>[orig_patent_app_number] => 11044648
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/044648 | Multiply instructions for modular exponentiation | Jan 26, 2005 | Abandoned |
Array
(
[id] => 852483
[patent_doc_number] => 07383552
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-03
[patent_title] => 'Object manager for common information model'
[patent_app_type] => utility
[patent_app_number] => 11/004431
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8437
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/383/07383552.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004431
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004431 | Object manager for common information model | Dec 2, 2004 | Issued |
Array
(
[id] => 5778265
[patent_doc_number] => 20060106905
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-18
[patent_title] => 'Method for reducing memory size in logarithmic number system arithmetic units'
[patent_app_type] => utility
[patent_app_number] => 10/990405
[patent_app_country] => US
[patent_app_date] => 2004-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2317
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0106/20060106905.pdf
[firstpage_image] =>[orig_patent_app_number] => 10990405
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/990405 | Method for reducing memory size in logarithmic number system arithmetic units | Nov 16, 2004 | Abandoned |
| 10/986428 | Mixed-mode multiplier using hard and soft logic circuitry | Nov 9, 2004 | Abandoned |
Array
(
[id] => 5827846
[patent_doc_number] => 20060063165
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-23
[patent_title] => 'Method for linear amplification of RNA using high-heel primer'
[patent_app_type] => utility
[patent_app_number] => 10/984640
[patent_app_country] => US
[patent_app_date] => 2004-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5546
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0063/20060063165.pdf
[firstpage_image] =>[orig_patent_app_number] => 10984640
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/984640 | Method for linear amplification of RNA using high-heel primer | Nov 8, 2004 | Abandoned |
Array
(
[id] => 7035813
[patent_doc_number] => 20050033788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'Method and apparatus for inverse discrete cosine transform'
[patent_app_type] => utility
[patent_app_number] => 10/934043
[patent_app_country] => US
[patent_app_date] => 2004-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7790
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0033/20050033788.pdf
[firstpage_image] =>[orig_patent_app_number] => 10934043
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/934043 | Method and apparatus for inverse discrete cosine transform | Sep 2, 2004 | Issued |
Array
(
[id] => 469899
[patent_doc_number] => 07240348
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-03
[patent_title] => 'Suspending scenario generation method, server device, and program therefor'
[patent_app_type] => utility
[patent_app_number] => 10/899147
[patent_app_country] => US
[patent_app_date] => 2004-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 21
[patent_no_of_words] => 5585
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/240/07240348.pdf
[firstpage_image] =>[orig_patent_app_number] => 10899147
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/899147 | Suspending scenario generation method, server device, and program therefor | Jul 26, 2004 | Issued |