Search

Elli Peselev

Examiner (ID: 14966)

Most Active Art Unit
1623
Art Unit(s)
1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802
Total Applications
2819
Issued Applications
1823
Pending Applications
143
Abandoned Applications
853

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12244375 [patent_doc_number] => 20180077238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'SELECTING A DATA STORAGE RESOURCE OF A DISPERSED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 15/812706 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 61 [patent_no_of_words] => 43258 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812706 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812706
Selecting a data storage resource of a dispersed storage network Nov 13, 2017 Issued
Array ( [id] => 14297119 [patent_doc_number] => 10288682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Integrated electronic device having a test architecture, and test method thereof [patent_app_type] => utility [patent_app_number] => 15/813000 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6645 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813000 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813000
Integrated electronic device having a test architecture, and test method thereof Nov 13, 2017 Issued
Array ( [id] => 13501133 [patent_doc_number] => 20180302109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => METHOD AND APPARATUS FOR DECODING THREE-DIMENSIONAL TURBO PRODUCT CODE BASED ON CROSSING LAYERS [patent_app_type] => utility [patent_app_number] => 15/812061 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812061 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812061
Method and apparatus for decoding three-dimensional turbo product code based on crossing layers Nov 13, 2017 Issued
Array ( [id] => 15373407 [patent_doc_number] => 10528422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM) [patent_app_type] => utility [patent_app_number] => 15/810731 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3458 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810731 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810731
Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM) Nov 12, 2017 Issued
Array ( [id] => 14982529 [patent_doc_number] => 10445176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Memory system, memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/810335 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810335 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810335
Memory system, memory device and operating method thereof Nov 12, 2017 Issued
Array ( [id] => 12741271 [patent_doc_number] => 20180138924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SCHEDULING METHOD OF A PARITY CHECK MATRIX AND AN LDPC DECODER FOR PERFORMING SCHEDULING OF A PARITY CHECK MATRIX [patent_app_type] => utility [patent_app_number] => 15/809392 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809392 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/809392
Scheduling method of a parity check matrix and an LDPC decoder for performing scheduling of a parity check matrix Nov 9, 2017 Issued
Array ( [id] => 12236795 [patent_doc_number] => 20180069656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/806763 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 52205 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15806763 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/806763
Transmitting apparatus and signal processing method thereof Nov 7, 2017 Issued
Array ( [id] => 13272595 [patent_doc_number] => 10148388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-04 [patent_title] => Digital data mutation detector and controller in web application interface [patent_app_type] => utility [patent_app_number] => 15/799861 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10871 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799861 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799861
Digital data mutation detector and controller in web application interface Oct 30, 2017 Issued
Array ( [id] => 15416399 [patent_doc_number] => 20200028522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => Soft Output Decoding of Polar Codes [patent_app_type] => utility [patent_app_number] => 16/337952 [patent_app_country] => US [patent_app_date] => 2017-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16337952 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/337952
Soft output decoding of polar codes Sep 29, 2017 Issued
Array ( [id] => 12264457 [patent_doc_number] => 20180083654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'TWO BIT ERROR CORRECTION VIA A FIELD PROGRAMMABLE GATE ARRAY' [patent_app_type] => utility [patent_app_number] => 15/711877 [patent_app_country] => US [patent_app_date] => 2017-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6113 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15711877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/711877
Two bit error correction via a field programmable gate array Sep 20, 2017 Issued
Array ( [id] => 14081205 [patent_doc_number] => 20190089490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => ERROR CORRECTION FOR DATA PACKETS TRANSMITTED USING AN ASYNCHRONOUS CONNECTION-LESS COMMUNICATION LINK [patent_app_type] => utility [patent_app_number] => 15/710085 [patent_app_country] => US [patent_app_date] => 2017-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15710085 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/710085
Error correction for data packets transmitted using an asynchronous connection-less communication link Sep 19, 2017 Issued
Array ( [id] => 13350897 [patent_doc_number] => 20180226988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => MULTIPLE LOW DENSITY PARITY CHECK (LDPC) BASE GRAPH DESIGN [patent_app_type] => utility [patent_app_number] => 15/709400 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15709400 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/709400
Multiple low density parity check (LDPC) base graph design Sep 18, 2017 Issued
Array ( [id] => 14771063 [patent_doc_number] => 10396944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Low latency corrupt data tagging on a cross-chip link [patent_app_type] => utility [patent_app_number] => 15/708488 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5582 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708488 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/708488
Low latency corrupt data tagging on a cross-chip link Sep 18, 2017 Issued
Array ( [id] => 14078797 [patent_doc_number] => 20190088286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => PHASE SLIP RECOVERY [patent_app_type] => utility [patent_app_number] => 15/707396 [patent_app_country] => US [patent_app_date] => 2017-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15707396 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/707396
Phase slip recovery Sep 17, 2017 Issued
Array ( [id] => 15135489 [patent_doc_number] => 10481205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Robust secure testing of integrated circuits [patent_app_type] => utility [patent_app_number] => 15/704515 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6236 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704515 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704515
Robust secure testing of integrated circuits Sep 13, 2017 Issued
Array ( [id] => 15108897 [patent_doc_number] => 10475780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Level shifter spare cell [patent_app_type] => utility [patent_app_number] => 15/703995 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3158 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703995 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703995
Level shifter spare cell Sep 13, 2017 Issued
Array ( [id] => 12224428 [patent_doc_number] => 20180062788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'REGENERATIVE PLAYLOAD USING END-TO-END FEC PROTECTION' [patent_app_type] => utility [patent_app_number] => 15/690847 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13260 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690847 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690847
Regenerative payload using end-to-end FEC protection Aug 29, 2017 Issued
Array ( [id] => 12096101 [patent_doc_number] => 20170353194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'LDPC Post-Processor Architecture and Method for Low Error Floor Conditions' [patent_app_type] => utility [patent_app_number] => 15/686361 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14422 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686361 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686361
LDPC post-processor architecture and method for low error floor conditions Aug 24, 2017 Issued
Array ( [id] => 16738124 [patent_doc_number] => 10963780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Yield improvements for three-dimensionally stacked neural network accelerators [patent_app_type] => utility [patent_app_number] => 15/685672 [patent_app_country] => US [patent_app_date] => 2017-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6770 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15685672 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/685672
Yield improvements for three-dimensionally stacked neural network accelerators Aug 23, 2017 Issued
Array ( [id] => 15317291 [patent_doc_number] => 10523367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Efficient survivor memory architecture for successive cancellation list decoding of channel polarization codes [patent_app_type] => utility [patent_app_number] => 15/680661 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680661 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/680661
Efficient survivor memory architecture for successive cancellation list decoding of channel polarization codes Aug 17, 2017 Issued
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