Search

Elli Peselev

Examiner (ID: 14966)

Most Active Art Unit
1623
Art Unit(s)
1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802
Total Applications
2819
Issued Applications
1823
Pending Applications
143
Abandoned Applications
853

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13497317 [patent_doc_number] => 20180300201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => BYPASSING ERROR CORRECTION CODE (ECC) PROCESSING BASED ON SOFTWARE HINT [patent_app_type] => utility [patent_app_number] => 15/489041 [patent_app_country] => US [patent_app_date] => 2017-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489041
Bypassing error correction code (ECC) processing based on software hint Apr 16, 2017 Issued
Array ( [id] => 13069009 [patent_doc_number] => 10055284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Systems and methods for providing error code detection using non-power-of-two flash cell mapping [patent_app_type] => utility [patent_app_number] => 15/489621 [patent_app_country] => US [patent_app_date] => 2017-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6716 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489621 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489621
Systems and methods for providing error code detection using non-power-of-two flash cell mapping Apr 16, 2017 Issued
Array ( [id] => 14368623 [patent_doc_number] => 10305633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Per-symbol K-bit interleaver [patent_app_type] => utility [patent_app_number] => 15/487041 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11700 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/487041
Per-symbol K-bit interleaver Apr 12, 2017 Issued
Array ( [id] => 11733639 [patent_doc_number] => 20170195083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'INFORMATION PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/465940 [patent_app_country] => US [patent_app_date] => 2017-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7366 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15465940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/465940
INFORMATION PROCESSING APPARATUS Mar 21, 2017 Abandoned
Array ( [id] => 11731403 [patent_doc_number] => 20170192846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'ERROR CORRECTION FOR NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 15/463395 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463395 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463395
Error correction for non-volatile memory Mar 19, 2017 Issued
Array ( [id] => 12242032 [patent_doc_number] => 20180074894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/455967 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 17879 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15455967 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/455967
Memory system Mar 9, 2017 Issued
Array ( [id] => 11758596 [patent_doc_number] => 20170205464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'Design-for-Test Techniques for a Digital Electronic Circuit' [patent_app_type] => utility [patent_app_number] => 15/455116 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 26638 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15455116 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/455116
Design-for-Test Techniques for a Digital Electronic Circuit Mar 8, 2017 Abandoned
Array ( [id] => 13417461 [patent_doc_number] => 20180260273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => DETECTION OF ERROR PATTERNS IN MEMORY DIES [patent_app_type] => utility [patent_app_number] => 15/454813 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15454813 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/454813
Detection of error patterns in memory dies Mar 8, 2017 Issued
Array ( [id] => 11960161 [patent_doc_number] => 20170264313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'LOW COMPLEXITY DECODER AND DECODING METHOD BASED ON CODE OF BIT NODE' [patent_app_type] => utility [patent_app_number] => 15/452906 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6166 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452906 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452906
LOW COMPLEXITY DECODER AND DECODING METHOD BASED ON CODE OF BIT NODE Mar 7, 2017 Abandoned
Array ( [id] => 14302247 [patent_doc_number] => 10291261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Early selection decoding and automatic tuning [patent_app_type] => utility [patent_app_number] => 15/453126 [patent_app_country] => US [patent_app_date] => 2017-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453126 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453126
Early selection decoding and automatic tuning Mar 7, 2017 Issued
Array ( [id] => 14009105 [patent_doc_number] => 10223011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Storage device including nonvolatile memory device and controller and operating method of the storage device [patent_app_type] => utility [patent_app_number] => 15/438644 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 13995 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438644 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/438644
Storage device including nonvolatile memory device and controller and operating method of the storage device Feb 20, 2017 Issued
Array ( [id] => 13376247 [patent_doc_number] => 20180239665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => PRIORITIZED ERROR-DETECTION AND SCHEDULING [patent_app_type] => utility [patent_app_number] => 15/438479 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438479 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/438479
Prioritized error-detection and scheduling Feb 20, 2017 Issued
Array ( [id] => 13185701 [patent_doc_number] => 10108370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Methods of reading nonvolatile memory devices [patent_app_type] => utility [patent_app_number] => 15/435389 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 12013 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15435389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/435389
Methods of reading nonvolatile memory devices Feb 16, 2017 Issued
Array ( [id] => 12262349 [patent_doc_number] => 20180081545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'RESISTANCE VARIABLE MEMORY APPARATUS, AND CIRCUIT AND METHOD FOR OPERATING THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/434784 [patent_app_country] => US [patent_app_date] => 2017-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11193 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15434784 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/434784
Resistance variable memory apparatus, and circuit and method for operating therefor Feb 15, 2017 Issued
Array ( [id] => 13895015 [patent_doc_number] => 10200066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Code reconstruction scheme for multiple code rate TPC decoder [patent_app_type] => utility [patent_app_number] => 15/433850 [patent_app_country] => US [patent_app_date] => 2017-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15433850 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/433850
Code reconstruction scheme for multiple code rate TPC decoder Feb 14, 2017 Issued
Array ( [id] => 14364123 [patent_doc_number] => 10303364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Techniques for low-latency chase decoding of turbo product codes with soft information [patent_app_type] => utility [patent_app_number] => 15/431561 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431561 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431561
Techniques for low-latency chase decoding of turbo product codes with soft information Feb 12, 2017 Issued
Array ( [id] => 13809187 [patent_doc_number] => 10181863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Semiconductor devices and semiconductor systems [patent_app_type] => utility [patent_app_number] => 15/429897 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5446 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15429897 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/429897
Semiconductor devices and semiconductor systems Feb 9, 2017 Issued
Array ( [id] => 12155483 [patent_doc_number] => 20180026748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'HEADER PROCESSING DEVICE, PROCESSOR, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/428347 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4239 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15428347 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/428347
Header processing device, processor, and electronic device Feb 8, 2017 Issued
Array ( [id] => 11651319 [patent_doc_number] => 20170147220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'DETERMINING WHETHER TO COMPRESS A DATA SEGMENT IN A DISPERSED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 15/427860 [patent_app_country] => US [patent_app_date] => 2017-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6702 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15427860 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/427860
Determining whether to compress a data segment in a dispersed storage network Feb 7, 2017 Issued
Array ( [id] => 13974475 [patent_doc_number] => 10216594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Automated stalled process detection and recovery [patent_app_type] => utility [patent_app_number] => 15/424978 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15424978 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/424978
Automated stalled process detection and recovery Feb 5, 2017 Issued
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