Search

Elli Peselev

Examiner (ID: 14966)

Most Active Art Unit
1623
Art Unit(s)
1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802
Total Applications
2819
Issued Applications
1823
Pending Applications
143
Abandoned Applications
853

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16181287 [patent_doc_number] => 20200228256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => HYBRID AUTOMATIC REPEAT REQUEST (HARQ) IN LISTEN BEFORE TALK SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/787328 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787328 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/787328
Hybrid automatic repeat request (HARQ) in listen before talk systems Feb 10, 2020 Issued
Array ( [id] => 17269229 [patent_doc_number] => 11194655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Storage controller and storage device including the same [patent_app_type] => utility [patent_app_number] => 16/775587 [patent_app_country] => US [patent_app_date] => 2020-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16775587 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/775587
Storage controller and storage device including the same Jan 28, 2020 Issued
Array ( [id] => 17138257 [patent_doc_number] => 11139830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Bit inversion for data transmission [patent_app_type] => utility [patent_app_number] => 16/774472 [patent_app_country] => US [patent_app_date] => 2020-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4746 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774472 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/774472
Bit inversion for data transmission Jan 27, 2020 Issued
Array ( [id] => 17269230 [patent_doc_number] => 11194656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 16/774609 [patent_app_country] => US [patent_app_date] => 2020-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 11279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774609 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/774609
Memory system Jan 27, 2020 Issued
Array ( [id] => 17209503 [patent_doc_number] => 11169876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Apparatuses, systems, and methods for error correction [patent_app_type] => utility [patent_app_number] => 16/748595 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748595 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/748595
Apparatuses, systems, and methods for error correction Jan 20, 2020 Issued
Array ( [id] => 16944800 [patent_doc_number] => 11057059 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-06 [patent_title] => Content aware bit flipping decoder [patent_app_type] => utility [patent_app_number] => 16/744061 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744061 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744061
Content aware bit flipping decoder Jan 14, 2020 Issued
Array ( [id] => 16957904 [patent_doc_number] => 11061767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Post-ECC CRC for DDR CRC retry performance improvement [patent_app_type] => utility [patent_app_number] => 16/736815 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736815 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/736815
Post-ECC CRC for DDR CRC retry performance improvement Jan 7, 2020 Issued
Array ( [id] => 17003239 [patent_doc_number] => 11082070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Channel interleaving method and apparatus [patent_app_type] => utility [patent_app_number] => 16/728020 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 11188 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728020 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728020
Channel interleaving method and apparatus Dec 26, 2019 Issued
Array ( [id] => 16488524 [patent_doc_number] => 20200382137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => MEMORY SYSTEMS AND METHODS OF CORRECTNG ERRORS IN THE MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/726693 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726693 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/726693
Memory systems and methods of correcting errors in the memory systems Dec 23, 2019 Issued
Array ( [id] => 16772063 [patent_doc_number] => 10983163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-20 [patent_title] => Function verification system for boundary scan test controller and method thereof [patent_app_type] => utility [patent_app_number] => 16/721732 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4784 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721732 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721732
Function verification system for boundary scan test controller and method thereof Dec 18, 2019 Issued
Array ( [id] => 16116527 [patent_doc_number] => 20200210286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SOFT CHIPKILL RECOVERY FOR BITLINE FAILURES [patent_app_type] => utility [patent_app_number] => 16/717857 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717857 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717857
Soft chipkill recovery for bitline failures Dec 16, 2019 Issued
Array ( [id] => 15777651 [patent_doc_number] => 20200119843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PROVIDE EARLY WARNING AND FAIL DETECTION [patent_app_type] => utility [patent_app_number] => 16/715162 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715162 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715162
Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection Dec 15, 2019 Issued
Array ( [id] => 16758560 [patent_doc_number] => 10977109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Apparatus including safety logic [patent_app_type] => utility [patent_app_number] => 16/704045 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 9846 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704045
Apparatus including safety logic Dec 4, 2019 Issued
Array ( [id] => 15743549 [patent_doc_number] => 20200110663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => REDUNDANT STORAGE OF ERROR CORRECTION CODE (ECC) CHECKBITS FOR VALIDATING PROPER OPERATION OF A STATIC RANDOM ACCESS MEMORY (SRAM) [patent_app_type] => utility [patent_app_number] => 16/703672 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703672
Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM) Dec 3, 2019 Issued
Array ( [id] => 16159307 [patent_doc_number] => 20200217886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => CIRCUIT TESTING SYSTEM AND CIRCUIT TESTING METHOD [patent_app_type] => utility [patent_app_number] => 16/701571 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701571 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/701571
Circuit testing system and circuit testing method Dec 2, 2019 Issued
Array ( [id] => 17003237 [patent_doc_number] => 11082068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Error correction circuit, memory controller having error correction circuit, and memory system having memory controller [patent_app_type] => utility [patent_app_number] => 16/694987 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694987 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694987
Error correction circuit, memory controller having error correction circuit, and memory system having memory controller Nov 24, 2019 Issued
Array ( [id] => 16022899 [patent_doc_number] => 20200186293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => METHOD AND APPARATUS FOR HYBRID AUTOMATIC REPEAT REQUEST IN NON-TERRESTRIAL NETWORK [patent_app_type] => utility [patent_app_number] => 16/692401 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692401 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692401
Method and apparatus for hybrid automatic repeat request in non-terrestrial network Nov 21, 2019 Issued
Array ( [id] => 16959729 [patent_doc_number] => 11063614 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-13 [patent_title] => Polar decoder processor [patent_app_type] => utility [patent_app_number] => 16/690575 [patent_app_country] => US [patent_app_date] => 2019-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 27814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16690575 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/690575
Polar decoder processor Nov 20, 2019 Issued
Array ( [id] => 15627161 [patent_doc_number] => 20200083985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => APPARATUS AND METHOD FOR CHANNEL ENCODING/DECODING IN COMMUNICATION OR BROADCASTING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/685193 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 408 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685193
Apparatus and method for channel encoding/decoding in communication or broadcasting system Nov 14, 2019 Issued
Array ( [id] => 16826392 [patent_doc_number] => 20210141685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => SYSTEM AND METHOD FOR IMPROVING EFFICIENCY AND REDUCING SYSTEM RESOURCE CONSUMPTION IN A DATA INTEGRITY CHECK [patent_app_type] => utility [patent_app_number] => 16/682726 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8838 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682726 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682726
System and method for improving efficiency and reducing system resource consumption in a data integrity check Nov 12, 2019 Issued
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