Elli Peselev
Examiner (ID: 14966)
Most Active Art Unit | 1623 |
Art Unit(s) | 1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802 |
Total Applications | 2819 |
Issued Applications | 1823 |
Pending Applications | 143 |
Abandoned Applications | 853 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 11770157
[patent_doc_number] => 09378846
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-28
[patent_title] => 'Non-mounted storage test device based on FPGA'
[patent_app_type] => utility
[patent_app_number] => 14/453652
[patent_app_country] => US
[patent_app_date] => 2014-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2802
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 335
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453652
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/453652 | Non-mounted storage test device based on FPGA | Aug 6, 2014 | Issued |
Array
(
[id] => 10651140
[patent_doc_number] => 09367392
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-14
[patent_title] => 'NAND flash memory having internal ECC processing and method of operation thereof'
[patent_app_type] => utility
[patent_app_number] => 14/450188
[patent_app_country] => US
[patent_app_date] => 2014-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 8074
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 328
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14450188
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/450188 | NAND flash memory having internal ECC processing and method of operation thereof | Jul 31, 2014 | Issued |
Array
(
[id] => 9859936
[patent_doc_number] => 20150039952
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-05
[patent_title] => 'CIRCUIT ARRANGEMENT AND METHOD WITH MODIFIED ERROR SYNDROME FOR ERROR DETECTION OF PERMANENT ERRORS IN MEMORIES'
[patent_app_type] => utility
[patent_app_number] => 14/447806
[patent_app_country] => US
[patent_app_date] => 2014-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 21860
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14447806
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/447806 | Circuit arrangement and method with modified error syndrome for error detection of permanent errors in memories | Jul 30, 2014 | Issued |
Array
(
[id] => 10218603
[patent_doc_number] => 20150103596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-16
[patent_title] => 'CODING METHOD AND DECODING METHOD IN MEMORY SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 14/446350
[patent_app_country] => US
[patent_app_date] => 2014-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 12718
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14446350
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/446350 | Coding method and decoding method in memory system | Jul 29, 2014 | Issued |
Array
(
[id] => 11452216
[patent_doc_number] => 09575862
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-02-21
[patent_title] => 'Integrated circuits with error handling capabilities'
[patent_app_type] => utility
[patent_app_number] => 14/333408
[patent_app_country] => US
[patent_app_date] => 2014-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8369
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14333408
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/333408 | Integrated circuits with error handling capabilities | Jul 15, 2014 | Issued |
Array
(
[id] => 11540122
[patent_doc_number] => 09614548
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-04-04
[patent_title] => 'Systems and methods for hybrid message passing and bit flipping decoding of LDPC codes'
[patent_app_type] => utility
[patent_app_number] => 14/326095
[patent_app_country] => US
[patent_app_date] => 2014-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 9069
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326095
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/326095 | Systems and methods for hybrid message passing and bit flipping decoding of LDPC codes | Jul 7, 2014 | Issued |
Array
(
[id] => 10493778
[patent_doc_number] => 20150378801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-31
[patent_title] => 'Systems and Methods for Fast Bit Error Rate Estimation'
[patent_app_type] => utility
[patent_app_number] => 14/318310
[patent_app_country] => US
[patent_app_date] => 2014-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 10883
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318310
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/318310 | Systems and methods for fast bit error rate estimation | Jun 26, 2014 | Issued |
Array
(
[id] => 10439270
[patent_doc_number] => 20150324282
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'SOLID-STATE MEMORY CORRUPTION MITIGATION'
[patent_app_type] => utility
[patent_app_number] => 14/312144
[patent_app_country] => US
[patent_app_date] => 2014-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6124
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14312144
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/312144 | Solid-state memory corruption mitigation | Jun 22, 2014 | Issued |
Array
(
[id] => 10022989
[patent_doc_number] => 09065486
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-23
[patent_title] => 'Detection, avoidance and/or correction of problematic puncturing patterns in parity bit streams used when implementing turbo codes'
[patent_app_type] => utility
[patent_app_number] => 14/300734
[patent_app_country] => US
[patent_app_date] => 2014-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 12640
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14300734
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/300734 | Detection, avoidance and/or correction of problematic puncturing patterns in parity bit streams used when implementing turbo codes | Jun 9, 2014 | Issued |
Array
(
[id] => 11080189
[patent_doc_number] => 20160277151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-22
[patent_title] => 'Transmission method and device based on management data input/output multi-source agreements'
[patent_app_type] => utility
[patent_app_number] => 15/032580
[patent_app_country] => US
[patent_app_date] => 2014-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 6037
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15032580
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/032580 | Transmission method and device based on management data input/output multi-source agreements | May 28, 2014 | Issued |
Array
(
[id] => 10462212
[patent_doc_number] => 20150347227
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-03
[patent_title] => 'Marker Programming in Non-Volatile Memories'
[patent_app_type] => utility
[patent_app_number] => 14/289311
[patent_app_country] => US
[patent_app_date] => 2014-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11397
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14289311
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/289311 | Marker programming in non-volatile memories | May 27, 2014 | Issued |
Array
(
[id] => 10603886
[patent_doc_number] => 09324455
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-26
[patent_title] => 'Apparatus for measuring signal skew of asynchronous flash memory controller'
[patent_app_type] => utility
[patent_app_number] => 14/288362
[patent_app_country] => US
[patent_app_date] => 2014-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3843
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14288362
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/288362 | Apparatus for measuring signal skew of asynchronous flash memory controller | May 26, 2014 | Issued |
Array
(
[id] => 10078836
[patent_doc_number] => 09116684
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-25
[patent_title] => 'Performing a cyclic redundancy checksum operation responsive to a user-level instruction'
[patent_app_type] => utility
[patent_app_number] => 14/288261
[patent_app_country] => US
[patent_app_date] => 2014-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5322
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14288261
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/288261 | Performing a cyclic redundancy checksum operation responsive to a user-level instruction | May 26, 2014 | Issued |
Array
(
[id] => 10099707
[patent_doc_number] => 09136022
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-15
[patent_title] => 'Selection of data for redundancy calculation by likely error rate'
[patent_app_type] => utility
[patent_app_number] => 14/285052
[patent_app_country] => US
[patent_app_date] => 2014-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 28
[patent_no_of_words] => 8730
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14285052
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/285052 | Selection of data for redundancy calculation by likely error rate | May 21, 2014 | Issued |
Array
(
[id] => 10948646
[patent_doc_number] => 20140351667
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-27
[patent_title] => 'METHOD OF DECODING A CORRECTING CODE, FOR EXAMPLE A TURBO-CODE, BY ANALYSIS OF THE EXTENDED SPECTRUM OF THE WORDS OF THE CODE'
[patent_app_type] => utility
[patent_app_number] => 14/285160
[patent_app_country] => US
[patent_app_date] => 2014-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4557
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14285160
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/285160 | Method of decoding a correcting code, for example a turbo-code, by analysis of the extended spectrum of the words of the code | May 21, 2014 | Issued |
Array
(
[id] => 13258507
[patent_doc_number] => 10141954
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-11-27
[patent_title] => Data error correcting method and device, and computer storage medium
[patent_app_type] => utility
[patent_app_number] => 15/108936
[patent_app_country] => US
[patent_app_date] => 2014-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 7309
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15108936
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/108936 | Data error correcting method and device, and computer storage medium | May 19, 2014 | Issued |
Array
(
[id] => 10042662
[patent_doc_number] => 09083382
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-14
[patent_title] => 'Memory with on-chip error correction'
[patent_app_type] => utility
[patent_app_number] => 14/281843
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 9520
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281843
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/281843 | Memory with on-chip error correction | May 18, 2014 | Issued |
Array
(
[id] => 11765635
[patent_doc_number] => 09374108
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-21
[patent_title] => 'Convolution-encoded hyper-speed channel with robust trellis error-correction'
[patent_app_type] => utility
[patent_app_number] => 14/281398
[patent_app_country] => US
[patent_app_date] => 2014-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 4952
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281398
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/281398 | Convolution-encoded hyper-speed channel with robust trellis error-correction | May 18, 2014 | Issued |
Array
(
[id] => 14123311
[patent_doc_number] => 10248514
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-02
[patent_title] => Method for performing failsafe calculations
[patent_app_type] => utility
[patent_app_number] => 15/302777
[patent_app_country] => US
[patent_app_date] => 2014-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5235
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15302777
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/302777 | Method for performing failsafe calculations | May 7, 2014 | Issued |
Array
(
[id] => 9999049
[patent_doc_number] => 09043666
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-26
[patent_title] => 'Method for efficient control signaling of two codeword to one codeword transmission'
[patent_app_type] => utility
[patent_app_number] => 14/270376
[patent_app_country] => US
[patent_app_date] => 2014-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 10546
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14270376
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/270376 | Method for efficient control signaling of two codeword to one codeword transmission | May 5, 2014 | Issued |