Search

Elli Peselev

Examiner (ID: 14966)

Most Active Art Unit
1623
Art Unit(s)
1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802
Total Applications
2819
Issued Applications
1823
Pending Applications
143
Abandoned Applications
853

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10130993 [patent_doc_number] => 09164829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Read bias management to reduce read errors for phase change memory' [patent_app_type] => utility [patent_app_number] => 14/269869 [patent_app_country] => US [patent_app_date] => 2014-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14269869 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/269869
Read bias management to reduce read errors for phase change memory May 4, 2014 Issued
Array ( [id] => 10433859 [patent_doc_number] => 20150318871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'ERROR CORRECTION WITH SECONDARY MEMORY' [patent_app_type] => utility [patent_app_number] => 14/266202 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14266202 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/266202
Error correction with secondary memory Apr 29, 2014 Issued
Array ( [id] => 10433860 [patent_doc_number] => 20150318873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'ITERATIVE DECODER WITH CONFIGURABLE POOL OF DECODING STAGES' [patent_app_type] => utility [patent_app_number] => 14/265387 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4187 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265387 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/265387
ITERATIVE DECODER WITH CONFIGURABLE POOL OF DECODING STAGES Apr 29, 2014 Abandoned
Array ( [id] => 10948651 [patent_doc_number] => 20140351672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'MISCORRECTION DETECTION FOR ERROR CORRECTING CODES USING BIT RELIABILITIES' [patent_app_type] => utility [patent_app_number] => 14/265249 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8525 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265249 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/265249
Miscorrection detection for error correcting codes using bit reliabilities Apr 28, 2014 Issued
Array ( [id] => 10956375 [patent_doc_number] => 20140359397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'MEMORY ACCESS APPARATUS AND METHOD FOR INTERLEAVING AND DEINTERLEAVING' [patent_app_type] => utility [patent_app_number] => 14/262936 [patent_app_country] => US [patent_app_date] => 2014-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4107 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14262936 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/262936
MEMORY ACCESS APPARATUS AND METHOD FOR INTERLEAVING AND DEINTERLEAVING Apr 27, 2014 Abandoned
Array ( [id] => 10284403 [patent_doc_number] => 20150169401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'DECODING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLING CIRCUIT UNIT' [patent_app_type] => utility [patent_app_number] => 14/264040 [patent_app_country] => US [patent_app_date] => 2014-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16475 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264040 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/264040
Decoding method, memory storage device, and memory controlling circuit unit Apr 27, 2014 Issued
Array ( [id] => 11810775 [patent_doc_number] => 09715345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Apparatuses and methods for memory management' [patent_app_type] => utility [patent_app_number] => 14/261956 [patent_app_country] => US [patent_app_date] => 2014-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 7717 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14261956 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/261956
Apparatuses and methods for memory management Apr 24, 2014 Issued
Array ( [id] => 11770080 [patent_doc_number] => 09378765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Systems and methods for differential message scaling in a decoding process' [patent_app_type] => utility [patent_app_number] => 14/261333 [patent_app_country] => US [patent_app_date] => 2014-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14261333 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/261333
Systems and methods for differential message scaling in a decoding process Apr 23, 2014 Issued
Array ( [id] => 11181621 [patent_doc_number] => 09413631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Communication circuit, physical quantity measurement device, electronic apparatus, moving object, and communication method' [patent_app_type] => utility [patent_app_number] => 14/259412 [patent_app_country] => US [patent_app_date] => 2014-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 10910 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14259412 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/259412
Communication circuit, physical quantity measurement device, electronic apparatus, moving object, and communication method Apr 22, 2014 Issued
Array ( [id] => 11877188 [patent_doc_number] => 09748973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Interleaved layered decoder for low-density parity check codes' [patent_app_type] => utility [patent_app_number] => 14/258843 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 9245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258843 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258843
Interleaved layered decoder for low-density parity check codes Apr 21, 2014 Issued
Array ( [id] => 10956377 [patent_doc_number] => 20140359399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'STORAGE INTEGRITY VALIDATOR' [patent_app_type] => utility [patent_app_number] => 14/258335 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258335 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258335
Storage integrity validator Apr 21, 2014 Issued
Array ( [id] => 10543501 [patent_doc_number] => 09268633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Guard interval signaling for data symbol number determination' [patent_app_type] => utility [patent_app_number] => 14/257817 [patent_app_country] => US [patent_app_date] => 2014-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7792 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14257817 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/257817
Guard interval signaling for data symbol number determination Apr 20, 2014 Issued
Array ( [id] => 11775199 [patent_doc_number] => 09384128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Multi-level redundancy code for non-volatile memory controller' [patent_app_type] => utility [patent_app_number] => 14/256268 [patent_app_country] => US [patent_app_date] => 2014-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 18547 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14256268 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/256268
Multi-level redundancy code for non-volatile memory controller Apr 17, 2014 Issued
Array ( [id] => 10922280 [patent_doc_number] => 20140325300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/256444 [patent_app_country] => US [patent_app_date] => 2014-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1794 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14256444 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/256444
Semiconductor device Apr 17, 2014 Issued
Array ( [id] => 10914454 [patent_doc_number] => 20140317472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'ENCODER, DECODER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/254012 [patent_app_country] => US [patent_app_date] => 2014-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5186 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14254012 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/254012
Encoder, decoder and semiconductor device including the same Apr 15, 2014 Issued
Array ( [id] => 10583515 [patent_doc_number] => 09305639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Read-detection in multi-level cell memory' [patent_app_type] => utility [patent_app_number] => 14/251734 [patent_app_country] => US [patent_app_date] => 2014-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9388 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14251734 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/251734
Read-detection in multi-level cell memory Apr 13, 2014 Issued
Array ( [id] => 10907566 [patent_doc_number] => 20140310580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'Cyclic Decoding for Cascaded Forward Error-Correction FEC Codes' [patent_app_type] => utility [patent_app_number] => 14/249609 [patent_app_country] => US [patent_app_date] => 2014-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1885 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14249609 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/249609
Cyclic decoding for cascaded forward error-correction FEC codes Apr 9, 2014 Issued
Array ( [id] => 10401516 [patent_doc_number] => 20150286525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'MEMORY ACCESS SCHEME FOR SYSTEM ON CHIP' [patent_app_type] => utility [patent_app_number] => 14/246140 [patent_app_country] => US [patent_app_date] => 2014-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2741 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14246140 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/246140
Memory access scheme for system on chip Apr 5, 2014 Issued
Array ( [id] => 10618410 [patent_doc_number] => 09337864 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-10 [patent_title] => 'Non-binary LDPC decoder using binary subgroup processing' [patent_app_type] => utility [patent_app_number] => 14/231511 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14231511 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/231511
Non-binary LDPC decoder using binary subgroup processing Mar 30, 2014 Issued
Array ( [id] => 10393004 [patent_doc_number] => 20150278011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'METHOD AND APPARATUS FOR MANAGING A SPIN TRANSFER TORQUE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/228555 [patent_app_country] => US [patent_app_date] => 2014-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13195 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14228555 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/228555
Method and apparatus for managing a spin transfer torque memory Mar 27, 2014 Issued
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