Search

Elli Peselev

Examiner (ID: 14966)

Most Active Art Unit
1623
Art Unit(s)
1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802
Total Applications
2819
Issued Applications
1823
Pending Applications
143
Abandoned Applications
853

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10625257 [patent_doc_number] => 09344217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Devices and methods for reconstructing corrupted control channel bits' [patent_app_type] => utility [patent_app_number] => 14/220973 [patent_app_country] => US [patent_app_date] => 2014-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11186 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14220973 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/220973
Devices and methods for reconstructing corrupted control channel bits Mar 19, 2014 Issued
Array ( [id] => 11206807 [patent_doc_number] => 09436434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Checksum adder' [patent_app_type] => utility [patent_app_number] => 14/211383 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14211383 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/211383
Checksum adder Mar 13, 2014 Issued
Array ( [id] => 10052482 [patent_doc_number] => 09092362 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-28 [patent_title] => 'Programmable data write management system and method for operating the same in a solid state drive' [patent_app_type] => utility [patent_app_number] => 14/210020 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 14497 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14210020 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/210020
Programmable data write management system and method for operating the same in a solid state drive Mar 12, 2014 Issued
Array ( [id] => 9563898 [patent_doc_number] => 20140181611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'System and Method for Mitigating Burst Noise in a Communications System' [patent_app_type] => utility [patent_app_number] => 14/194922 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14194922 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/194922
System and method for mitigating burst noise in a communications system Mar 2, 2014 Issued
Array ( [id] => 10344332 [patent_doc_number] => 20150229337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'MITIGATION OF WRITE ERRORS IN MULTI-LEVEL CELL FLASH MEMORY THROUGH ADAPTIVE ERROR CORRECTION CODE DECODING' [patent_app_type] => utility [patent_app_number] => 14/194180 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14194180 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/194180
Mitigation of write errors in multi-level cell flash memory through adaptive error correction code decoding Feb 27, 2014 Issued
Array ( [id] => 9912211 [patent_doc_number] => 20150067415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'MEMORY SYSTEM AND CONSTRUCTING METHOD OF LOGICAL BLOCK' [patent_app_type] => utility [patent_app_number] => 14/193452 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8367 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14193452 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/193452
Memory system and constructing method of logical block Feb 27, 2014 Issued
Array ( [id] => 10125994 [patent_doc_number] => 09160369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-13 [patent_title] => 'Method for iterative error correction with designed error floor performance' [patent_app_type] => utility [patent_app_number] => 14/192041 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2338 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192041 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/192041
Method for iterative error correction with designed error floor performance Feb 26, 2014 Issued
Array ( [id] => 9758875 [patent_doc_number] => 20140289576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR SELF TEST OF SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/192810 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14192810 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/192810
SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR SELF TEST OF SEMICONDUCTOR INTEGRATED CIRCUIT Feb 26, 2014 Abandoned
Array ( [id] => 10610755 [patent_doc_number] => 09330792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Testing memory devices with distributed processing operations' [patent_app_type] => utility [patent_app_number] => 14/191342 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5015 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14191342 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/191342
Testing memory devices with distributed processing operations Feb 25, 2014 Issued
Array ( [id] => 10526291 [patent_doc_number] => 09252817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Dynamic log-likelihood ratio mapping for error correcting code decoding' [patent_app_type] => utility [patent_app_number] => 14/189850 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 20881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189850 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189850
Dynamic log-likelihood ratio mapping for error correcting code decoding Feb 24, 2014 Issued
Array ( [id] => 9673447 [patent_doc_number] => 20140237310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'Test Architecture for Characterizing Interconnects in Stacked Designs' [patent_app_type] => utility [patent_app_number] => 14/183305 [patent_app_country] => US [patent_app_date] => 2014-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3904 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14183305 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/183305
Test architecture for characterizing interconnects in stacked designs Feb 17, 2014 Issued
Array ( [id] => 10172836 [patent_doc_number] => 09203555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Optimum signal constellation design and mapping for few-mode fiber based LDPC-coded CO-OFDM' [patent_app_type] => utility [patent_app_number] => 14/179683 [patent_app_country] => US [patent_app_date] => 2014-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3694 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14179683 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/179683
Optimum signal constellation design and mapping for few-mode fiber based LDPC-coded CO-OFDM Feb 12, 2014 Issued
Array ( [id] => 10530358 [patent_doc_number] => 09256494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Memory system and operating method thereof' [patent_app_type] => utility [patent_app_number] => 14/177970 [patent_app_country] => US [patent_app_date] => 2014-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177970 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/177970
Memory system and operating method thereof Feb 10, 2014 Issued
Array ( [id] => 10027791 [patent_doc_number] => 09069693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Decoder based data recovery' [patent_app_type] => utility [patent_app_number] => 14/176624 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14176624 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/176624
Decoder based data recovery Feb 9, 2014 Issued
Array ( [id] => 10344320 [patent_doc_number] => 20150229325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'ENCODING FOR PARTITIONED DATA BUS' [patent_app_type] => utility [patent_app_number] => 14/175394 [patent_app_country] => US [patent_app_date] => 2014-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13360 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14175394 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/175394
Encoding for partitioned data bus Feb 6, 2014 Issued
Array ( [id] => 10004893 [patent_doc_number] => 09048997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Apparatus and method using matrix network coding' [patent_app_type] => utility [patent_app_number] => 14/172186 [patent_app_country] => US [patent_app_date] => 2014-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7888 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14172186 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/172186
Apparatus and method using matrix network coding Feb 3, 2014 Issued
Array ( [id] => 9513337 [patent_doc_number] => 20140149830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'APPARATUS AND METHOD USING MATRIX NETWORK CODING' [patent_app_type] => utility [patent_app_number] => 14/172133 [patent_app_country] => US [patent_app_date] => 2014-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7866 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14172133 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/172133
Apparatus and method using matrix network coding Feb 3, 2014 Issued
Array ( [id] => 10555657 [patent_doc_number] => 09279855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Semiconductor integtrated circuit including test pads' [patent_app_type] => utility [patent_app_number] => 14/167700 [patent_app_country] => US [patent_app_date] => 2014-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8223 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14167700 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/167700
Semiconductor integtrated circuit including test pads Jan 28, 2014 Issued
Array ( [id] => 9980555 [patent_doc_number] => 09026886 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-05 [patent_title] => 'Methods and systems for reconfigurable LDPC decoders' [patent_app_type] => utility [patent_app_number] => 14/167699 [patent_app_country] => US [patent_app_date] => 2014-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5617 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14167699 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/167699
Methods and systems for reconfigurable LDPC decoders Jan 28, 2014 Issued
Array ( [id] => 10329976 [patent_doc_number] => 20150214980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'Method and Apparatus of a Fully-Pipelined Layered LDPC Decoder' [patent_app_type] => utility [patent_app_number] => 14/165505 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14165505 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/165505
Method and apparatus of a fully-pipelined layered LDPC decoder Jan 26, 2014 Issued
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