Search

Elli Peselev

Examiner (ID: 14966)

Most Active Art Unit
1623
Art Unit(s)
1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802
Total Applications
2819
Issued Applications
1823
Pending Applications
143
Abandoned Applications
853

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9847757 [patent_doc_number] => 08949692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-03 [patent_title] => 'Method and system for service-aware parity placement in a storage system' [patent_app_type] => utility [patent_app_number] => 14/162250 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7673 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162250
Method and system for service-aware parity placement in a storage system Jan 22, 2014 Issued
Array ( [id] => 10003098 [patent_doc_number] => 09047191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Error control in memory storage systems' [patent_app_type] => utility [patent_app_number] => 14/151442 [patent_app_country] => US [patent_app_date] => 2014-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9594 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14151442 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/151442
Error control in memory storage systems Jan 8, 2014 Issued
Array ( [id] => 9599191 [patent_doc_number] => 20140195872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'SIMULTANEOUS DATA TRANSFER AND ERROR CONTROL TO REDUCE LATENCY AND IMPROVE THROUGHPUT TO A HOST' [patent_app_type] => utility [patent_app_number] => 14/150667 [patent_app_country] => US [patent_app_date] => 2014-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14150667 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/150667
Simultaneous data transfer and error control to reduce latency and improve throughput to a host Jan 7, 2014 Issued
Array ( [id] => 10303517 [patent_doc_number] => 20150188517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'CHIP PADS' [patent_app_type] => utility [patent_app_number] => 14/144759 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5357 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144759 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/144759
Integrated circuit operating active circuitry and chip pads in different operating modes and at different voltage levels Dec 30, 2013 Issued
Array ( [id] => 9567833 [patent_doc_number] => 20140185546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'METHOD AND APPARATUS FOR PROCESSING A DOWNLINK SHARED CHANNEL' [patent_app_type] => utility [patent_app_number] => 14/139037 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4536 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139037 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/139037
Method and apparatus for processing a downlink shared channel Dec 22, 2013 Issued
Array ( [id] => 9866731 [patent_doc_number] => 20150046750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'ERROR DETECTION CIRCUIT AND DATA PROCESSING APPARATUS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/092141 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4625 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14092141 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/092141
Error detection circuit and data processing apparatus using the same Nov 26, 2013 Issued
Array ( [id] => 10250035 [patent_doc_number] => 20150135031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'DYNAMIC PER-DECODER CONTROL OF LOG LIKELIHOOD RATIO AND DECODING PARAMETERS' [patent_app_type] => utility [patent_app_number] => 14/092215 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8685 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14092215 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/092215
Dynamic per-decoder control of log likelihood ratio and decoding parameters Nov 26, 2013 Issued
Array ( [id] => 10125091 [patent_doc_number] => 09159458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Flash interface error injector' [patent_app_type] => utility [patent_app_number] => 14/090059 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2902 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090059 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/090059
Flash interface error injector Nov 25, 2013 Issued
Array ( [id] => 10524483 [patent_doc_number] => 09250998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Cache structure with parity-protected clean data and ECC-protected dirty data' [patent_app_type] => utility [patent_app_number] => 14/090427 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9313 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090427 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/090427
Cache structure with parity-protected clean data and ECC-protected dirty data Nov 25, 2013 Issued
Array ( [id] => 10264871 [patent_doc_number] => 20150149869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'PHYSICAL SUBSECTOR ERROR MARKING' [patent_app_type] => utility [patent_app_number] => 14/090984 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090984 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/090984
Physical subsector error marking Nov 25, 2013 Issued
Array ( [id] => 10524518 [patent_doc_number] => 09251034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Device performance monitoring' [patent_app_type] => utility [patent_app_number] => 14/089424 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089424 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/089424
Device performance monitoring Nov 24, 2013 Issued
Array ( [id] => 9800851 [patent_doc_number] => 20150012795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'ERROR CORRECTION DECODER AND ERROR CORRECTION DECODING METHOD' [patent_app_type] => utility [patent_app_number] => 14/087487 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8964 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087487 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087487
Error correction decoder and error correction decoding method Nov 21, 2013 Issued
Array ( [id] => 10152564 [patent_doc_number] => 09184871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Method for network coding for cooperative relay network in wireless communication system' [patent_app_type] => utility [patent_app_number] => 14/087921 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3124 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087921 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087921
Method for network coding for cooperative relay network in wireless communication system Nov 21, 2013 Issued
Array ( [id] => 10529838 [patent_doc_number] => 09255968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Integrated circuit with a high-speed debug access port' [patent_app_type] => utility [patent_app_number] => 14/087690 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087690 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087690
Integrated circuit with a high-speed debug access port Nov 21, 2013 Issued
Array ( [id] => 9520588 [patent_doc_number] => 20140157081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'WIRELESS RECEIVER CIRCUIT AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/086814 [patent_app_country] => US [patent_app_date] => 2013-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5002 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14086814 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/086814
Wireless receiver circuit and method Nov 20, 2013 Issued
Array ( [id] => 9365397 [patent_doc_number] => 20140075270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'APPARATUS AND METHOD USING MATRIX NETWORK CODING' [patent_app_type] => utility [patent_app_number] => 14/083912 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7849 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/083912
Apparatus and method using matrix network coding Nov 18, 2013 Issued
Array ( [id] => 10249617 [patent_doc_number] => 20150134613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'Systems and Methods for Lost Synchronization Data Set Reprocessing' [patent_app_type] => utility [patent_app_number] => 14/080935 [patent_app_country] => US [patent_app_date] => 2013-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14080935 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/080935
Systems and methods for lost synchronization data set reprocessing Nov 14, 2013 Issued
Array ( [id] => 10501406 [patent_doc_number] => 09229806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Block closure techniques for a data storage device' [patent_app_type] => utility [patent_app_number] => 14/080626 [patent_app_country] => US [patent_app_date] => 2013-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14080626 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/080626
Block closure techniques for a data storage device Nov 13, 2013 Issued
Array ( [id] => 10250042 [patent_doc_number] => 20150135038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'POST PACKAGE REPAIR OF MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/077630 [patent_app_country] => US [patent_app_date] => 2013-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8894 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14077630 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/077630
Post package repair of memory devices Nov 11, 2013 Issued
Array ( [id] => 11308364 [patent_doc_number] => 09515775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Method and apparatus for improving the performance of TCP and other network protocols in a communication network' [patent_app_type] => utility [patent_app_number] => 14/400541 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16106 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14400541 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/400541
Method and apparatus for improving the performance of TCP and other network protocols in a communication network Nov 6, 2013 Issued
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