Search

Elli Peselev

Examiner (ID: 14966)

Most Active Art Unit
1623
Art Unit(s)
1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802
Total Applications
2819
Issued Applications
1823
Pending Applications
143
Abandoned Applications
853

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9926375 [patent_doc_number] => 08984361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Protocols for multi-hop relay system with centralized scheduling' [patent_app_type] => utility [patent_app_number] => 13/859835 [patent_app_country] => US [patent_app_date] => 2013-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859835 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/859835
Protocols for multi-hop relay system with centralized scheduling Apr 9, 2013 Issued
Array ( [id] => 9745984 [patent_doc_number] => 20140281703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Local Repair Signature Handling for Repairable Memories' [patent_app_type] => utility [patent_app_number] => 13/859507 [patent_app_country] => US [patent_app_date] => 2013-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5632 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859507 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/859507
Local Repair Signature Handling for Repairable Memories Apr 8, 2013 Abandoned
Array ( [id] => 10873332 [patent_doc_number] => 08898552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Communication system with blind decoding mechanism and method of operation thereof' [patent_app_type] => utility [patent_app_number] => 13/859177 [patent_app_country] => US [patent_app_date] => 2013-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 15245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859177 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/859177
Communication system with blind decoding mechanism and method of operation thereof Apr 8, 2013 Issued
Array ( [id] => 9891642 [patent_doc_number] => 08977917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Highly secure and extensive scan testing of integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/858422 [patent_app_country] => US [patent_app_date] => 2013-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13858422 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/858422
Highly secure and extensive scan testing of integrated circuits Apr 7, 2013 Issued
Array ( [id] => 9787752 [patent_doc_number] => 20140304573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'TRANSIENT CONDITION MANAGEMENT UTILIZING A POSTED ERROR DETECTION PROCESSING PROTOCOL' [patent_app_type] => utility [patent_app_number] => 13/856937 [patent_app_country] => US [patent_app_date] => 2013-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11462 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13856937 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/856937
Transient condition management utilizing a posted error detection processing protocol Apr 3, 2013 Issued
Array ( [id] => 9980563 [patent_doc_number] => 09026894 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-05 [patent_title] => 'Channel decoder and method for generating equalized data and data estimates based on multiple sets of depths provided via a viterbi algorithm' [patent_app_type] => utility [patent_app_number] => 13/854510 [patent_app_country] => US [patent_app_date] => 2013-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13854510 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/854510
Channel decoder and method for generating equalized data and data estimates based on multiple sets of depths provided via a viterbi algorithm Mar 31, 2013 Issued
Array ( [id] => 9006248 [patent_doc_number] => 20130227373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'Impulse and/or burst noise signal to noise ratio (SNR) aware concatenated forward error correction (FEC)' [patent_app_type] => utility [patent_app_number] => 13/853486 [patent_app_country] => US [patent_app_date] => 2013-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13853486 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/853486
Impulse and/or burst noise signal to noise ratio (SNR) aware concatenated forward error correction (FEC) Mar 28, 2013 Issued
Array ( [id] => 9992725 [patent_doc_number] => 09037945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoder' [patent_app_type] => utility [patent_app_number] => 13/852852 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 2861 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852852 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/852852
Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoder Mar 27, 2013 Issued
Array ( [id] => 9992728 [patent_doc_number] => 09037949 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-19 [patent_title] => 'Error correction in a memory device' [patent_app_type] => utility [patent_app_number] => 13/846200 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 11151 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13846200 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/846200
Error correction in a memory device Mar 17, 2013 Issued
Array ( [id] => 10016715 [patent_doc_number] => 09059742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-16 [patent_title] => 'System and method for dynamic scaling of LDPC decoder in a solid state drive' [patent_app_type] => utility [patent_app_number] => 13/842956 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3514 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13842956 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/842956
System and method for dynamic scaling of LDPC decoder in a solid state drive Mar 14, 2013 Issued
Array ( [id] => 8941817 [patent_doc_number] => 20130191614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-25 [patent_title] => 'PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 13/796032 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13796032 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/796032
Performing a cyclic redundancy checksum operation responsive to a user-level instruction Mar 11, 2013 Issued
Array ( [id] => 10047212 [patent_doc_number] => 09087612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'DRAM error detection, evaluation, and correction' [patent_app_type] => utility [patent_app_number] => 13/780205 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3234 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13780205 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/780205
DRAM error detection, evaluation, and correction Feb 27, 2013 Issued
Array ( [id] => 8893789 [patent_doc_number] => 20130166973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'STORAGE-MEDIUM DIAGNOSIS DEVICE, STORAGE-MEDIUM DIAGNOSIS METHOD' [patent_app_type] => utility [patent_app_number] => 13/770318 [patent_app_country] => US [patent_app_date] => 2013-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9659 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13770318 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/770318
Storage-medium diagnosis device, storage-medium diagnosis method Feb 18, 2013 Issued
Array ( [id] => 9540173 [patent_doc_number] => 20140164819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'MEMORY OPERATION OF PAIRED MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/769472 [patent_app_country] => US [patent_app_date] => 2013-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6120 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13769472 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/769472
Memory operation of paired memory devices Feb 17, 2013 Issued
Array ( [id] => 10171806 [patent_doc_number] => 09202518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Combined soft detection/soft decoding in tape drive storage channels' [patent_app_type] => utility [patent_app_number] => 13/762216 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 10252 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762216 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762216
Combined soft detection/soft decoding in tape drive storage channels Feb 6, 2013 Issued
Array ( [id] => 8893803 [patent_doc_number] => 20130166987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices' [patent_app_type] => utility [patent_app_number] => 13/753579 [patent_app_country] => US [patent_app_date] => 2013-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 62 [patent_no_of_words] => 22602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13753579 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/753579
LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices Jan 29, 2013 Issued
Array ( [id] => 8843388 [patent_doc_number] => 20130139016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF CONTROLLING THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND INFORMATION PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/749079 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13749079 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/749079
Semiconductor integrated circuit device, method of controlling the semiconductor integrated circuit device and information processing system Jan 23, 2013 Issued
Array ( [id] => 9611731 [patent_doc_number] => 08788920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Detection, avoidance and/or correction of problematic puncturing patterns in parity bit streams used when implementing turbo codes' [patent_app_type] => utility [patent_app_number] => 13/744984 [patent_app_country] => US [patent_app_date] => 2013-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12625 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13744984 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/744984
Detection, avoidance and/or correction of problematic puncturing patterns in parity bit streams used when implementing turbo codes Jan 17, 2013 Issued
Array ( [id] => 9665923 [patent_doc_number] => 08812934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Techniques for storing bits in memory cells having stuck-at faults' [patent_app_type] => utility [patent_app_number] => 13/712956 [patent_app_country] => US [patent_app_date] => 2012-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4956 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13712956 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/712956
Techniques for storing bits in memory cells having stuck-at faults Dec 11, 2012 Issued
Array ( [id] => 9507133 [patent_doc_number] => 08745463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Error correcting codes for increased storage capacity in multilevel memory devices' [patent_app_type] => utility [patent_app_number] => 13/712880 [patent_app_country] => US [patent_app_date] => 2012-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4401 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13712880 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/712880
Error correcting codes for increased storage capacity in multilevel memory devices Dec 11, 2012 Issued
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