Elli Peselev
Examiner (ID: 14966)
Most Active Art Unit | 1623 |
Art Unit(s) | 1673, 2899, 1623, 1621, 1203, 1803, 1211, 1802 |
Total Applications | 2819 |
Issued Applications | 1823 |
Pending Applications | 143 |
Abandoned Applications | 853 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 10873323
[patent_doc_number] => 08898544
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-25
[patent_title] => 'DRAM error detection, evaluation, and correction'
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[patent_app_number] => 13/710561
[patent_app_country] => US
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13710561
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/710561 | DRAM error detection, evaluation, and correction | Dec 10, 2012 | Issued |
Array
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[id] => 8827790
[patent_doc_number] => 20130128835
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-23
[patent_title] => 'METHOD AND APPARATUS FOR PROCESSING A DOWNLINK SHARED CHANNEL'
[patent_app_type] => utility
[patent_app_number] => 13/711501
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/711501 | Method and apparatus for processing a downlink shared channel | Dec 10, 2012 | Issued |
Array
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[id] => 9207725
[patent_doc_number] => 20140006902
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-02
[patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING ECC CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/711024
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[patent_app_date] => 2012-12-11
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/711024 | Semiconductor device including ECC circuit | Dec 10, 2012 | Issued |
Array
(
[id] => 9540207
[patent_doc_number] => 20140164854
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[patent_kind] => A1
[patent_issue_date] => 2014-06-12
[patent_title] => 'pBIST ARCHITECTURE WITH MULTIPLE ASYNCHRONOUS SUB CHIPS OPERATING IN DIFFERRING VOLTAGE DOMAINS'
[patent_app_type] => utility
[patent_app_number] => 13/709168
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[patent_app_date] => 2012-12-10
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/709168 | pBIST architecture with multiple asynchronous sub chips operating in differing voltage domains | Dec 9, 2012 | Issued |
Array
(
[id] => 9879035
[patent_doc_number] => 08966331
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[patent_kind] => B2
[patent_issue_date] => 2015-02-24
[patent_title] => 'Test circuit of semiconductor memory apparatus and semiconductor memory system including the same'
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Array
(
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[patent_doc_number] => 20140164844
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[patent_kind] => A1
[patent_issue_date] => 2014-06-12
[patent_title] => 'pBIST ENGINE WITH DISTRIBUTED DATA LOGGING'
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Array
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[patent_title] => 'Testing Disk Drives Shared by Multiple Processors in a Supercomputer Complex'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/709452 | Testing disk drives shared by multiple processors in a supercomputer complex | Dec 9, 2012 | Issued |
Array
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[id] => 9947641
[patent_doc_number] => 08996969
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[patent_kind] => B2
[patent_issue_date] => 2015-03-31
[patent_title] => 'Low density parity check decoder with miscorrection handling'
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[patent_app_number] => 13/708941
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/708941 | Low density parity check decoder with miscorrection handling | Dec 7, 2012 | Issued |
Array
(
[id] => 9540206
[patent_doc_number] => 20140164853
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-12
[patent_title] => 'MEMORY OPERATION OF PAIRED MEMORY DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/707675
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/707675 | Memory operation of paired memory devices | Dec 6, 2012 | Issued |
Array
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[patent_title] => 'Storing data in a distributed storage network'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/707471 | Storing data in a distributed storage network | Dec 5, 2012 | Issued |
Array
(
[id] => 9967921
[patent_doc_number] => 09015556
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[patent_issue_date] => 2015-04-21
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Array
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[id] => 10156865
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Array
(
[id] => 9879037
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Array
(
[id] => 9520580
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Array
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Array
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Array
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