Elli Peselev

Array ( [id] => 8831748 [patent_doc_number] => 20130132793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'ENCODING, DECODING, AND MULTI-STAGE DECODING CIRCUITS FOR CONCATENATED BCH, AND ERROR CORRECTION CIRCUIT OF FLASH MEMORY DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/678812 [patent_app_country] => US [patent_app_date] => 2012-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15393 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13678812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9474852 [patent_doc_number] => 20140132315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'INTEGRATED CIRCUIT WITH DEGRADATION MONITORING' [patent_app_type] => utility [patent_app_number] => 13/677800 [patent_app_country] => US [patent_app_date] => 2012-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13677800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10895076 [patent_doc_number] => 08918706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-23 [patent_title] => 'Methods and circuitry for performing parallel error checking' [patent_app_type] => utility [patent_app_number] => 13/677181 [patent_app_country] => US [patent_app_date] => 2012-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13677181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9834556 [patent_doc_number] => 08943390 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-27 [patent_title] => 'Peel decoding for concatenated codes' [patent_app_type] => utility [patent_app_number] => 13/676876 [patent_app_country] => US [patent_app_date] => 2012-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5149 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13676876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9707431 [patent_doc_number] => 08832525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Memory controller with low density parity check code decoding capability and relevant memory controlling method' [patent_app_type] => utility [patent_app_number] => 13/676822 [patent_app_country] => US [patent_app_date] => 2012-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13676822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10873320 [patent_doc_number] => 08898541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Storage controller, storage device, information processing system, and storage controlling method' [patent_app_type] => utility [patent_app_number] => 13/675768 [patent_app_country] => US [patent_app_date] => 2012-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 29806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13675768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8719490 [patent_doc_number] => 20130070707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'Signaling Reserved Hybrid Automatic Repeat Request Information for Downlink Semi-Persistent Scheduling' [patent_app_type] => utility [patent_app_number] => 13/666419 [patent_app_country] => US [patent_app_date] => 2012-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8855 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13666419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8661333 [patent_doc_number] => 20130042162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'CHAINED CHECKSUM ERROR CORRECTION MECHANISM TO IMPROVE TCP PERFORMANCE OVER NETWORK WITH WIRELESS LINKS' [patent_app_type] => utility [patent_app_number] => 13/652269 [patent_app_country] => US [patent_app_date] => 2012-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13652269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9410253 [patent_doc_number] => 20140101505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'CLOCK CONTROL FOR REDUCING TIMING EXCEPTIONS IN SCAN TESTING OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/645600 [patent_app_country] => US [patent_app_date] => 2012-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13645600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9410257 [patent_doc_number] => 20140101509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'Systems and Methods for Parallel Retry Processing During Iterative Data Processing' [patent_app_type] => utility [patent_app_number] => 13/644542 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13644542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9781395 [patent_doc_number] => 08856618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Scalable repair block error correction for sequential multiple data blocks in a magnetic data storage device' [patent_app_type] => utility [patent_app_number] => 13/645309 [patent_app_country] => US [patent_app_date] => 2012-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4140 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13645309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9398555 [patent_doc_number] => 20140095961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'LAYERED DECODER ENHANCEMENT FOR RETAINED SECTOR REPROCESSING' [patent_app_type] => utility [patent_app_number] => 13/644181 [patent_app_country] => US [patent_app_date] => 2012-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7397 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13644181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9940831 [patent_doc_number] => 08990662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Techniques for resilient communication' [patent_app_type] => utility [patent_app_number] => 13/631937 [patent_app_country] => US [patent_app_date] => 2012-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3581 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13631937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10507071 [patent_doc_number] => 09234942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Transition fault testing of source synchronous interface' [patent_app_type] => utility [patent_app_number] => 13/624372 [patent_app_country] => US [patent_app_date] => 2012-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4852 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13624372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10860802 [patent_doc_number] => 08887021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Continuously interleaved error correction' [patent_app_type] => utility [patent_app_number] => 13/618380 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4324 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13618380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9341584 [patent_doc_number] => 20140068368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'LDPC Decoder With Fractional Unsatisfied Check Quality Metric' [patent_app_type] => utility [patent_app_number] => 13/602463 [patent_app_country] => US [patent_app_date] => 2012-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8650608 [patent_doc_number] => 20130036338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'METHOD FOR EFFICIENT CONTROL SIGNALING OF TWO CODEWORD TO ONE CODEWORD TRANSMISSION' [patent_app_type] => utility [patent_app_number] => 13/584686 [patent_app_country] => US [patent_app_date] => 2012-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10484 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13584686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9251913 [patent_doc_number] => 08615704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => 'Edge incremental redundancy memory structure and memory management' [patent_app_type] => utility [patent_app_number] => 13/571819 [patent_app_country] => US [patent_app_date] => 2012-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13571819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9765941 [patent_doc_number] => 08850289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Quality based priority data processing with soft guaranteed iteration' [patent_app_type] => utility [patent_app_number] => 13/560702 [patent_app_country] => US [patent_app_date] => 2012-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13560702 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8491497 [patent_doc_number] => 20120290904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'ERROR GENERATION DIRECTION CIRCUIT, STORAGE UNIT, INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF ERROR GENERATION DIRECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/558610 [patent_app_country] => US [patent_app_date] => 2012-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14016 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558610 [rel_patent_id] =>[rel_patent_doc_number] =>)